This is information on a product in full production. 

July 2024

DS13737 Rev 10

1/346

STM32U575xx

Ultra-low-power Arm

®

 Cortex

®

-M33 32-bit MCU+TrustZone

®

+FPU, 

240 DMIPS, up to 2 MB Flash memory, 786 KB SRAM

Datasheet 

-

 production data

Features

Includes ST state-of-the-art patented 
technology

Ultra-low-power with FlexPowerControl

1.71 V to 3.6 V power supply

–40 °C to +85/125 °C temperature range

Low-power background autonomous mode 
(LPBAM): autonomous peripherals with DMA, 
functional down to Stop 2 mode

V

BAT

 mode: supply for RTC, 32 x 32-bit backup 

registers and 2-Kbyte backup SRAM

160 nA Shutdown mode (24 wake-up pins)

210 nA Standby mode (24 wake-up pins) 

530 nA Standby mode with RTC

1.9 

μ

A Stop 3 mode with 16-Kbyte SRAM 

4.3 µA Stop 3 mode with full SRAM 

4.0 µA Stop 2 mode with 16-Kbyte SRAM

8.95 µA Stop 2 mode with full SRAM

19.5 

μ

A/MHz Run mode @ 3.3 V

Core

Arm

®

 32-bit Cortex

®

-M33 CPU with 

TrustZone

®

, MPU, DSP, and FPU

ART Accelerator

8-Kbyte instruction cache allowing 0-wait-state 
execution from flash and external memories: 
up to 160 MHz, 240 DMIPS

4-Kbyte data cache for external memories

Power management

Embedded regulator (LDO) and SMPS 
step-down converter supporting switch 
on-the-fly and voltage scaling

Benchmarks

1.5 DMIPS/MHz (Drystone 2.1)

651 CoreMark

® 

(4.07 CoreMark

®

/MHz)

450 ULPMark™-CP

109 ULPMark™-PP

51.5 ULPMark™-CM

133000 SecureMark™-TLS

Memories

2-Mbyte flash memory with ECC, 2 banks 
read-while-write, including 512 Kbytes with 
100 kcycles

786-Kbyte SRAM with ECC OFF or 722-Kbyte 
SRAM including up to 322-Kbyte SRAM with 
ECC ON

External memory interface supporting SRAM, 
PSRAM, NOR, NAND, and FRAM memories

2 Octo-SPI memory interfaces

Security

Arm

®

 TrustZone

®

 and securable I/Os, 

memories, and peripherals

Flexible life cycle scheme with RDP and 
password protected debug

Root of trust thanks to unique boot entry and 
secure hide protection area (HDP)

LQFP48 (7 x 7 mm)

LQFP64 (10 x 10 mm)

LQFP100 (14 x 14 mm)
LQFP144 (20 x 20 mm)

UFQFPN48

(7 x 7 mm)

WLCSP90

(4.2 x 3.95 mm)

UFBGA132

(7 x 7 mm)

UFBGA169

(7 x 7 mm)

Product label

www.st.com

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Secure firmware installation (SFI) thanks to 
embedded root secure services (RSS)

Secure firmware upgrade support with TF-M

HASH hardware accelerator

True random number generator, NIST 
SP800-90B compliant

96-bit unique ID

512-byte OTP (one-time programmable)

Active tampers

Clock management

4 to 50 MHz crystal oscillator

32 kHz crystal oscillator for RTC (LSE)

Internal 16 MHz factory-trimmed RC (±1%)

Internal low-power 32 kHz RC (±5%)

2 internal multispeed 100 kHz to 48 MHz 
oscillators, including one autotrimmed by LSE 
(better than ±0.25% accuracy)

Internal 48 MHz with clock recovery

3 PLLs for system clock, USB, audio, ADC

General-purpose input/outputs

Up to 136 fast I/Os with interrupt capability 
most 5V-tolerant and up to 14 I/Os with 
independent supply down to 1.08 V

Up to 17 timers and 2 watchdogs

2 16-bit advanced motor-control, 4 32-bit, 
5 16-bit, 4 low-power 16-bit (available in Stop 
mode), 2 SysTick timers and 2 watchdogs

RTC with hardware calendar and calibration

Up to 22 communication peripherals

1 USB Type-C

®

/USB power delivery controller

1 USB OTG 2.0 full-speed controller

2 SAIs (serial audio interface)

4 I2C FM+(1 Mbit/s), SMBus/PMBus

®

6 U(S)ART (SPI, ISO 7816, LIN, IrDA, modem)

3 SPI (+2 with OCTOSPI +3 with USART)

1 CAN FD controller 

2 SDMMC interfaces

1 multifunction digital filter (6 filters) + 1 audio 
digital filter with sound-activity detection

Parallel synchronous slave interface

16- and 4-channel DMA controllers, 
functional in Stop mode

Graphic features

Chrom-ART Accelerator (DMA2D) for 
enhanced graphic content creation

1 digital camera interface

Mathematical coprocessor

CORDIC for trigonometric functions 
acceleration

Filter mathematical accelerator (FMAC)

Up to 22 capacitive sensing channels

Support touch key, linear, and rotary touch 
sensors

Rich analog peripherals (independent 
supply)

14-bit ADC 2.5-Msps with hardware 
oversampling

12-bit ADC 2.5-Msps, with hardware 
oversampling, autonomous in Stop 2 mode

2 12-bit DAC, low-power sample and hold

2 operational amplifiers with built-in PGA

2 ultra-low-power comparators

CRC calculation unit
Debug

Development support: serial-wire debug 
(SWD), JTAG, Embedded Trace Macrocell™ 
(ETM)

ECOPACK2 compliant packages  

Table 1. Device summary

Reference

Part numbers

STM32U575xx

STM32U575AG, STM32U575AI, 
STM32U575CG, STM32U575CI, 
STM32U575OG, STM32U575OI, 
STM32U575QG, STM32U575QI, 
STM32U575RG, STM32U575RI, 
STM32U575VG, STM32U575VI, 
STM32U575ZG, STM32U575ZI

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Contents

8

Contents

1

Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3

Functional overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1

Arm Cortex-M33 core with TrustZone

 

and FPU  . . . . . . . . . . . . . . . . . . . .  22

3.2

ART Accelerator (ICACHE and DCACHE)  . . . . . . . . . . . . . . . . . . . . . . . .  22

3.2.1

Instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.2

Data cache (DCACHE)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3

Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24

3.4

Embedded flash memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24

3.4.1

Flash memory protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4.2

Additional flash memory protections when TrustZone activated  . . . . . . 27

3.4.3

FLASH privilege protection   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5

Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28

3.5.1

SRAMs TrustZone security   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5.2

SRAMs privilege protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.6

TrustZone security architecture  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29

3.6.1

TrustZone peripheral classification   . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.6.2

Default TrustZone security state   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.7

Boot modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30

3.8

Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33

3.9

Power supply management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33

3.9.1

Power supply schemes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.9.2

Power supply supervisor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.9.3

Low-power modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.9.4

Reset mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.9.5

VBAT operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.9.6

PWR TrustZone security  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.10

Peripheral interconnect matrix  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  47

3.11

Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  48

3.11.1

RCC TrustZone security   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.12

Clock recovery system (CRS)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  51

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3.13

General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . .  51

3.13.1

GPIOs TrustZone security  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.14

Low-power general-purpose inputs/outputs (LPGPIO)   . . . . . . . . . . . . . .  51

3.14.1

LPGPIO TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.15

Multi-AHB bus matrix  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  52

3.16

System configuration controller (SYSCFG)  . . . . . . . . . . . . . . . . . . . . . . .  52

3.17

General purpose direct memory access controller (GPDMA)   . . . . . . . . .  52

3.18

Low-power direct memory access controller (LPDMA)   . . . . . . . . . . . . . .  54

3.19

Chrom-ART Accelerator controller (DMA2D)  . . . . . . . . . . . . . . . . . . . . . .  56

3.20

Interrupts and events  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  57

3.20.1

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 57

3.20.2

Extended interrupt/event controller (EXTI)   . . . . . . . . . . . . . . . . . . . . . . 57

3.21

Cyclic redundancy check calculation unit (CRC)  . . . . . . . . . . . . . . . . . . .  58

3.22

CORDIC coprocessor (CORDIC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  58

3.23

Filter math accelerator (FMAC)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  58

3.24

Flexible static memory controller (FSMC)   . . . . . . . . . . . . . . . . . . . . . . . .  59

3.24.1

LCD parallel interface   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.24.2

FSMC TrustZone security   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.25

Octo-SPI interface (OCTOSPI)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  60

3.25.1

OCTOSPI TrustZone security   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.26

OCTOSPI I/O manager (OCTOSPIM)  . . . . . . . . . . . . . . . . . . . . . . . . . . .  61

3.27

Delay block (DLYB)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  61

3.28

Analog-to-digital converter (ADC1 and ADC4)  . . . . . . . . . . . . . . . . . . . . .  61

3.28.1

Analog-to-digital converter 1 (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.28.2

Analog-to-digital converter 4 (ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.28.3

Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.28.4

Internal voltage reference (VREFINT)  . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.28.5

VBAT battery voltage monitoring  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.29

Digital-to-analog converter (DAC)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  66

3.30

Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  67

3.31

Comparators (COMP)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  67

3.32

Operational amplifiers (OPAMP)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  68

3.33

Multifunction digital filter (MDF) and audio digital filter (ADF)   . . . . . . . . .  68

3.33.1

Multifunction digital filter (MDF)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.33.2

Audio digital filter (ADF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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3.34

Digital camera interface (DCMI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  72

3.35

Parallel synchronous slave interface (PSSI)   . . . . . . . . . . . . . . . . . . . . . .  72

3.36

Touch sensing controller (TSC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  72

3.37

True random number generator (RNG)  . . . . . . . . . . . . . . . . . . . . . . . . . .  73

3.38

HASH hardware accelerator (HASH)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  74

3.39

Timers and watchdogs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  75

3.39.1

Advanced-control timers (TIM1, TIM8)   . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.39.2

General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15,

 

TIM16, TIM17)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.39.3

Basic timers (TIM6 and TIM7)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.39.4

Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4) . . . . . . . . . . . . 76

3.39.5

Infrared interface (IRTIM)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.39.6

Independent watchdog (IWDG)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.39.7

Window watchdog (WWDG)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.39.8

SysTick timer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.40

Real-time clock (RTC), tamper and backup registers   . . . . . . . . . . . . . . .  78

3.40.1

Real-time clock (RTC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.40.2

Tamper and backup registers (TAMP)  . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.41

Inter-integrated circuit interface (I

2

C)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  80

3.42

Universal synchronous/asynchronous receiver transmitter (USART/UART)

 

and low-power universal asynchronous receiver transmitter (LPUART)  .  81

3.42.1

Universal synchronous/asynchronous receiver transmitter

 

(USART/UART)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.42.2

Low-power universal asynchronous receiver transmitter (LPUART)  . . . 83

3.43

Serial peripheral interface (SPI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  84

3.44

Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  85

3.45

Secure digital input/output and MultiMediaCards interface (SDMMC)  . . .  86

3.46

Controller area network (FDCAN)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  88

3.47

USB on-the-go full-speed (OTG_FS)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  88

3.48

USB Type-C /USB Power Delivery controller (UCPD)  . . . . . . . . . . . . . . .  90

3.49

Development support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  90

3.49.1

Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.49.2

Embedded Trace Macrocell  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4

Pinout, pin description and alternate functions . . . . . . . . . . . . . . . . . . 91

4.1

Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  91

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4.2

Pin description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  103

4.3

Alternate functions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  131

5

Electrical characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

5.1

Parameter conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  150

5.1.1

Minimum and maximum values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

5.1.2

Typical values   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

5.1.3

Typical curves   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

5.1.4

Loading capacitor   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

5.1.5

Pin input voltage   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

5.1.6

Power supply scheme  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

5.1.7

Current consumption measurement   . . . . . . . . . . . . . . . . . . . . . . . . . . 153

5.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  153

5.3

Operating conditions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  156

5.3.1

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

5.3.2

Operating conditions at power-up/power-down  . . . . . . . . . . . . . . . . . . 158

5.3.3

Embedded reset and power control block characteristics  . . . . . . . . . . 159

5.3.4

SMPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

5.3.5

Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

5.3.6

Supply current characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

5.3.7

Wake-up time from low-power modes and voltage scaling

 

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

5.3.8

External clock timing characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . 210

5.3.9

Internal clock timing characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

5.3.10

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

5.3.11

Flash memory characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

5.3.12

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

5.3.13

Electrical sensitivity characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

5.3.14

I/O current injection characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

5.3.15

I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

5.3.16

NRST pin characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

5.3.17

Extended interrupt and event controller input (EXTI) characteristics . . 239

5.3.18

Analog switches booster  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

5.3.19

14-bit analog-to-digital converter (ADC1) characteristics   . . . . . . . . . . 240

5.3.20

12-bit analog-to-digital converter (ADC4) characteristics   . . . . . . . . . . 246

5.3.21

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

5.3.22

V

CORE 

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

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5.3.23

V

BA

monitoring characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

5.3.24

Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 252

5.3.25

Voltage reference buffer characteristics   . . . . . . . . . . . . . . . . . . . . . . . 256

5.3.26

Comparator characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

5.3.27

Operational amplifiers characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . 260

5.3.28

Temperature and backup domain supply thresholds monitoring  . . . . . 263

5.3.29

ADF/MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

5.3.30

DCMI characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

5.3.31

PSSI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

5.3.32

Timer characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

5.3.33

FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

5.3.34

OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

5.3.35

SD/SDIO/

e

•MMC card host interfaces (SDMMC) characteristics  . . . . 292

5.3.36

Delay block characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

5.3.37

I2C interface characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

5.3.38

USART (SPI mode) characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

5.3.39

SPI characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

5.3.40

SAI characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

5.3.41

OTG_FS characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

5.3.42

UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

5.3.43

JTAG/SWD interface characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . 304

6

Package information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

6.1

UFQFPN48 package information (A0B9)  . . . . . . . . . . . . . . . . . . . . . . . .  307

6.2

LQFP48 package information (5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  310

6.3

LQFP64 package information (5W)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  314

6.4

WLCSP90 package information (B01C) . . . . . . . . . . . . . . . . . . . . . . . . .  318

6.5

LQFP100 package information (1L)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  321

6.6

UFBGA132 package information (A0G8)  . . . . . . . . . . . . . . . . . . . . . . . .  325

6.7

LQFP144 package information (1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  328

6.8

UFBGA169 package information (A0YV)  . . . . . . . . . . . . . . . . . . . . . . . .  333

6.9

Package thermal characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  336

6.9.1

Reference documents  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

7

Ordering information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

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8

Important security notice  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

9

Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

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List of tables

12

List of tables

Table 1.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2.

STM32U575xx features and peripheral counts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 3.

Access status versus protection level and execution modes when TZEN = 0 . . . . . . . . . . 25

Table 4.

Access status versus protection level and execution modes when TZEN = 1 . . . . . . . . . . 26

Table 5.

Example of memory map security attribution versus SAU configuration regions . . . . . . . . 29

Table 6.

Boot modes when TrustZone is disabled (TZEN = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 7.

Boot modes when TrustZone is enabled (TZEN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 8.

Boot space versus RDP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 9.

STM32U575xx mode overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 10.

Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 11.

GPDMA1 channels implementation and usage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 12.

GPDMA1 autonomous mode and wake-up in low-power modes . . . . . . . . . . . . . . . . . . . . 54

Table 13.

 LPDMA1 channels implementation and usage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 14.

LPDMA1 autonomous mode and wake-up in low-power modes  . . . . . . . . . . . . . . . . . . . . 56

Table 15.

ADC features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 16.

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 17.

Internal voltage reference calibration values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 18.

MDF features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 19.

Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 20.

I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 21.

USART, UART, and LPUART features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 22.

SPI features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 23.

SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 24.

SDMMC features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 25.

Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 26.

STM32U575xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 27.

Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 28.

Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 29.

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 30.

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 31.

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 32.

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 33.

Operating conditions at power-up/power-down  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 34.

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 35.

SMPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 36.

Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 37.

Current consumption in Run mode on LDO, code with data processing

 

running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 163

Table 38.

Current consumption in Run mode on SMPS, code with data processing

 

running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 164

Table 39.

Current consumption in Run mode on SMPS, code with data processing

 

running from Flash memory, ICACHE ON (1-way), prefetch ON, V

DD

 = 3.0 V  . . . . . . . . 165

Table 40.

Typical current consumption in Run mode on LDO, with different codes

 

running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON  . . . 166

Table 41.

Typical current consumption in Run mode on LDO, with different codes

 

running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 166

Table 42.

Typical current consumption in Run mode on SMPS, with different codes

 

running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON  . . . 168

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Table 43.

Typical current consumption in Run mode on SMPS, with different codes

 

running from Flash memory, ICACHE ON (1-way), prefetch ON . . . . . . . . . . . . . . . . . . . 168

Table 44.

Current consumption in Sleep mode on LDO, Flash memory in power down  . . . . . . . . . 170

Table 45.

Current consumption in Sleep mode on SMPS, Flash memory in power down . . . . . . . . 171

Table 46.

Current consumption in Sleep mode on SMPS, 

 

Flash memory in power down, V

DD

 = 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 47.

SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and SMPS . . . . . . . 173

Table 48.

Static power consumption of Flash banks, when supplied by LDO/SMPS . . . . . . . . . . . . 174

Table 49.

Current consumption in Stop 0 mode on LDO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 50.

Current consumption in Stop 0 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 51.

Current consumption in Stop 1 mode on LDO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 52.

Current consumption during wake-up from Stop 1 mode on LDO  . . . . . . . . . . . . . . . . . . 178

Table 53.

Current consumption in Stop 1 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 54.

Current consumption during wake-up from Stop 1 mode on SMPS . . . . . . . . . . . . . . . . . 180

Table 55.

Current consumption in Stop 2 mode on LDO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 56.

SRAM static power consumption in Stop 2 when supplied by LDO . . . . . . . . . . . . . . . . . 182

Table 57.

Current consumption during wake-up from Stop 2 mode on LDO  . . . . . . . . . . . . . . . . . . 183

Table 58.

Current consumption in Stop 2 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 59.

SRAM static power consumption in Stop 2 when supplied by SMPS. . . . . . . . . . . . . . . . 185

Table 60.

Current consumption during wake-up from Stop 2 mode on SMPS . . . . . . . . . . . . . . . . . 186

Table 61.

Current consumption in Stop 3 mode on LDO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 62.

SRAM static power consumption in Stop 3 when supplied by LDO . . . . . . . . . . . . . . . . . 188

Table 63.

Current consumption during wake-up from Stop 3 mode on LDO  . . . . . . . . . . . . . . . . . . 189

Table 64.

Current consumption in Stop 3 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 65.

SRAM static power consumption in Stop 3 when supplied by SMPS. . . . . . . . . . . . . . . . 191

Table 66.

Current consumption during wake-up from Stop 3 mode on SMPS . . . . . . . . . . . . . . . . . 192

Table 67.

Current consumption in Standby mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 68.

Current consumption during wake-up from Standby mode. . . . . . . . . . . . . . . . . . . . . . . . 196

Table 69.

Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 70.

Current consumption during wake-up from Shutdown mode . . . . . . . . . . . . . . . . . . . . . . 197

Table 71.

Current consumption in V

BAT

 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 72.

Typical dynamic current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 73.

Low-power mode wake-up timings on LDO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 74.

Low-power mode wake-up timings on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 75.

Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 76.

Wake-up time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 77.

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 78.

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 79.

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 80.

LSE oscillator characteristics (f

LSE

 = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 81.

HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 82.

MSI oscillator characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Table 83.

HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table 84.

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 85.

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 86.

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table 87.

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 88.

EMS characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 89.

EMI characteristics for f

HSE

 = 8 MHz and f

HCLK

 = 160 MHz. . . . . . . . . . . . . . . . . . . . . . . 226

Table 90.

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 91.

Electrical sensitivities  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 92.

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

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Table 93.

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 94.

Output voltage characteristics (all I/Os except FT_t I/Os in VBAT mode,

 

and FT_o I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 95.

Output voltage characteristics for FT_t I/Os in V

BAT

 mode, and for FT_o I/Os  . . . . . . . . 232

Table 96.

Output AC characteristics, HSLV OFF (all I/Os except FT_c,

 

FT_t in VBAT mode and FT_o I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Table 97.

Output AC characteristics, HSLV ON (all I/Os except FT_c)  . . . . . . . . . . . . . . . . . . . . . . 235

Table 98.

Output AC characteristics for FT_c I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 99.

Output AC characteristics for FT_t I/Os in V

BAT

 mode, and for FT_o I/Os . . . . . . . . . . . . 237

Table 100. NRST pin characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 101. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 102. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 103. 14-bit ADC1 characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 104. Maximum RAIN for 14-bit ADC1   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 105. 14-bit ADC1 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 106. 12-bit ADC4 characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 107. Maximum RAIN for 12-bit ADC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 108. 12-bit ADC4 accuracy  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 109. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 110. V

CORE

 monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Table 111. V

BAT

 monitoring characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Table 112. V

BAT

 charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Table 113. DAC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 114. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 115. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 116. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 117. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 118. ADF characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 119. MDF characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 120. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 121. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 122. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 123. TIMx characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Table 124. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 125. WWDG min/max timeout value at 160 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 126. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings  . . . . . . . . . . . . . . . . . 273
Table 127. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 273
Table 128. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 274
Table 129. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 275
Table 130. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 131. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 276
Table 132. Asynchronous multiplexed PSRAM/NOR write timings  . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 133. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 278
Table 134. Synchronous multiplexed NOR/PSRAM read timings  . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 135. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 136. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 137. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 138. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 139. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 140. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 141. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Table 142. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus  . . . . . . . . . . . . . . . . . . . . 288

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Table 143. SD/e•MMC characteristics (V

DD

 = 2.7 V to 3.6 V)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Table 144. e•MMC characteristics (V

DD

 = 1.71 V to 1.9 V)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Table 145. Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 146. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 147. USART (SPI mode) characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 148. SPI characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Table 149. SAI characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 150. OTG_FS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 151. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 152. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 153. SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Table 154. UFQFPN48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 155. LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Table 156. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Table 157. WLCSP90 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Table 158. WLCSP90 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Table 159. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Table 160. UFBGA132 - Mechanical data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Table 161. UFBGA132 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 326
Table 162. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Table 163. UFBGA169 - Mechanical data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Table 164. UFBGA169 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 334
Table 165. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Table 166. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

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15

List of figures

Figure 1.

STM32U575xx block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 2.

STM32U575xQ power supply overview (with SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 3.

STM32U575xx power supply overview (without SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 4.

Power-up /down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 5.

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 6.

VREFBUF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 7.

LQFP48_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 8.

LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 9.

UFQFPN48_SMPS pinout  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 10.

UFQFPN48 pinout  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 11.

LQFP64_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 12.

LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 13.

WLCSP90_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 14.

LQFP100_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 15.

LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 16.

UFBGA132_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 17.

UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 18.

LQFP144_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 19.

LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 20.

UFBGA169_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 21.

UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 22.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 23.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 24.

STM32U575xx power supply scheme (without SMPS)  . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 25.

STM32U575xQ power supply scheme (with SMPS)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 26.

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 27.

VREFINT versus temperature  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 28.

AC timing diagram for high-speed external clock source (digital mode). . . . . . . . . . . . . . 211

Figure 29.

AC timing diagram for high-speed external clock source (analog mode) . . . . . . . . . . . . . 212

Figure 30.

AC timing diagram for low-speed external square clock source . . . . . . . . . . . . . . . . . . . . 212

Figure 31.

AC timing diagram for low-speed external sinusoidal clock source  . . . . . . . . . . . . . . . . . 213

Figure 32.

Typical application with a 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Figure 33.

Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Figure 34.

HSI16 frequency versus temperature and V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Figure 35.

HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 36.

I/O input characteristics (all I/Os except BOOT0 and FT_c). . . . . . . . . . . . . . . . . . . . . . . 231

Figure 37.

Output AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Figure 38.

Recommended NRST pin protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 39.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 40.

Typical connection diagram when using the ADC

 

with FT/TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 41.

12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 42.

V

REFBUF_OUT

 versus temperature (VRS = 000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 43.

V

REFBUF_OUT

 versus temperature (VRS = 001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 44.

V

REFBUF_OUT

 versus temperature (VRS = 010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 45.

V

REFBUF_OUT

 versus temperature (VRS = 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 46.

OPAMP voltage noise density, normal mode, R

LOAD

 = 3.9 k

 . . . . . . . . . . . . . . . . . . . . 263

Figure 47.

OPAMP voltage noise density, low-power mode, R

LOAD

 = 20 k

 . . . . . . . . . . . . . . . . . . 263

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Figure 48.

ADF timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 49.

MDF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 50.

DCMI timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 51.

PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Figure 52.

PSSI receive timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 53.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms  . . . . . . . . . . . . . . 272

Figure 54.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 274

Figure 55.

Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 275

Figure 56.

Asynchronous multiplexed PSRAM/NOR write waveforms  . . . . . . . . . . . . . . . . . . . . . . . 277

Figure 57.

Synchronous multiplexed NOR/PSRAM read timings  . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 58.

Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 59.

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 60.

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Figure 61.

NAND controller waveforms for read access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Figure 62.

NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Figure 63.

NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 285

Figure 64.

NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 285

Figure 65.

OCTOSPI timing diagram - SDR mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Figure 66.

OCTOSPI timing diagram - DDR mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Figure 67.

OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Figure 68.

OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 69.

OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 70.

OCTOSPI HyperBus write  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 71.

SD high-speed mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Figure 72.

SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Figure 73.

SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Figure 74.

USART timing diagram in SPI master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Figure 75.

USART timing diagram in SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 76.

SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 77.

SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 78.

SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 79.

SAI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Figure 80.

SAI slave timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Figure 81.

JTAG timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Figure 82.

SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Figure 83.

UFQFPN48 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 84.

UFQFPN48 – Footprint example  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Figure 85.

UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Figure 86.

LQFP48 - Outline

(15)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 87.

LQFP48 - Footprint example  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 88.

LQFP48 marking example (package top view)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 89.

LQFP64 - Outline

(15)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Figure 90.

LQFP64 - Footprint example  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

Figure 91.

LQFP64 marking example (package top view)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 92.

WLCSP90 - Outline  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Figure 93.

WLCSP90 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Figure 94.

WLCSP90 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Figure 95.

LQFP100 - Outline

(15)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Figure 96.

LQFP100 - Footprint example  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Figure 97.

LQFP100 marking example (package top view)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Figure 98.

UFBGA132 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Figure 99.

UFBGA132 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

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List of figures

15

Figure 100. UFBGA132 marking example (package top view)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Figure 101. LQFP144 - Outline

(15)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Figure 102. LQFP144 - Footprint example  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Figure 103. LQFP144 marking example (package top view)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 104. UFBGA169 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 105. UFBGA169 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Figure 106. UFBGA169 marking example (package top view)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

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1 Introduction

This document provides the ordering information and mechanical device characteristics of 
the STM32U575xx microcontrollers.
For information on the Arm

®(a)

 Cortex

®

-M33 core, refer to the Cortex

®

-M33 Technical 

reference manual, available from the www.arm.com website.

For information on the device errata with respect to the datasheet and reference manual, 
refer to the STM32U575xx and STM32U585xx errata sheet (ES0499).

          

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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21

2 Description

The STM32U575xx devices belong to an ultra-low-power microcontrollers family 
(STM32U5 series) based on the high-performance Arm

®

 Cortex

®

-M33 32-bit RISC core. 

They operate at a frequency of up to 160 MHz. 

The Cortex

®

-M33 core features a single-precision FPU (floating-point unit), that supports all 

the Arm

®

 single-precision data-processing instructions and all the data types. 

The Cortex

®

-M33 core also implements a full set of DSP (digital signal processing) 

instructions and a MPU (memory protection unit) that enhances the application security.

The devices embed high-speed memories (up to 2 Mbytes of flash memory and 786 Kbytes 
of SRAM), an FSMC (flexible external memory controller) for static memories (for devices 
with packages of 90 pins and more), two Octo-SPI flash memory interfaces (at least one 
Quad-SPI available on all packages) and an extensive range of enhanced I/Os and 
peripherals connected to three APB buses, three AHB buses and a 32-bit multi-AHB bus 
matrix.

The devices offer security foundation compliant with the TBSA (trusted-based security 
architecture) requirements from Arm

®

. It embeds the necessary security features to 

implement a secure boot, secure data storage and secure firmware update. Besides these 
capabilities, the devices incorporate a secure firmware installation feature that allows the 
customer to secure the provisioning of the code during its production. A flexible lifecycle is 
managed thanks to multiple levels of readout protection and debug unlock with password. 
Firmware hardware isolation is supported thanks to securable peripherals, memories and 
I/Os, and privilege configuration of peripherals and memories.

The devices feature several protection mechanisms for embedded flash memory and 
SRAM: readout protection, write protection, secure, and hide protection areas.

The devices embed several peripherals reinforcing security:  a HASH hardware accelerator, 
and a true random number generator.

The devices offer active tamper detection and protection against transient and 
environmental perturbation attacks, thanks to several internal monitoring generating secret 
data erase in case of attack. This helps to fit the PCI requirements for point of sales 
applications. 

The devices offer one fast 14-bit ADC (2.5 Msps), one 12-bit ADC (2.5 Msps), two 
comparators, two operational amplifiers, two DAC channels, an internal voltage reference 
buffer, a low-power RTC, four 32-bit general-purpose timers, two 16-bit PWM timers 
dedicated to motor control, three 16-bit general-purpose timers, two 16-bit basic timers and 
four 16-bit low-power timers. 

The devices support an MDF (multifunction digital filter) with six filters dedicated to the 
connection of external sigma-delta modulators. Another low-power digital filter dedicated to 
audio signals is embedded (ADF), with one filter supporting sound-activity detection. The 
devices embed also a Chrom-ART Accelerator dedicated to graphic applications, and 
mathematical accelerators (a trigonometric functions accelerator plus a filter mathematical 
accelerator). In addition, up to 22 capacitive sensing channels are available. 

The devices also feature standard and advanced communication interfaces such as: 
four I

2

Cs, three SPIs, three USARTs, two UARTs, one low-power UART, two SAIs, one 

digital camera interface (DCMI), two SDMMCs, one FDCAN, one USB OTG full-speed, 

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one USB Type-C /USB Power Delivery controller, and one generic synchronous 8-/16-bit 
PSSI (parallel data input/output slave interface).

The devices operate in the –40 to +85 °C (+105 °C junction) and –40 to +125 °C 
(+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. 

A comprehensive set of power-saving modes allow the design of low-power applications. 
Many peripherals (including communication, analog, timers, and audio peripherals) can be 
functional and autonomous down to Stop mode with direct memory access, thanks to 
LPBAM support (low-power background autonomous mode).

Some independent power supplies are supported like an analog independent supply input 
for ADC, DACs, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and 
up to 14 I/Os that can be supplied independently down to 1.08 V. A VBAT input is available 
for connecting a backup battery in order to preserve the RTC functionality and to backup 32

 

32-bit registers and 2-Kbyte SRAM. 

The devices offer eight packages from 48 to 169 pins.

          

Table 2. STM32U575xx features and peripheral counts 

Peripherals

STM32

U

575

CG/I 

STM32

U

575

RG/I 

ST

M32U

575OG/I 

STM32U575VG/I 

ST

M32U

575QG/I 

ST

M3

2U57

5ZG/I 

STM32

U

575

AG/I 

Flash memory (Mbytes)

1 (for STM32U575xG) - 2 (for STM32U575xI)

SRAM

System (Kbytes)

784 (192+64+512+16)

Backup (bytes)

2048 backup SRAM + 128 backup registers

External memory controller for 
static memories (FSMC)

No

Yes

(1)

Yes

(2)

OCTOSPI

2

(3)

2

Timers

Advanced control

2 (16 bits)

General purpose

4 (32 bits) and 3 (16 bits) 

Basic

2 (16 bits)

Low power

4 (16 bits)

SysTick timer

2

Watchdog timers 
(independent, 
window)

2

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STM32U575xx

Description

21

Communication 
interfaces

SPI 3

I2C

4

USART

3

UART

1

2

LPUART

1

SAI

1

2

FDCAN

1

OTG FS

Yes

UCPD

Yes

SDMMC

0

2

(4)

Camera interface

No

Yes/No

(5)

Yes

PSSI

No

Yes/No

(5)

Yes

MDF (multi-function digital filter)

Yes

(2 filters)

Yes

(6 filters)

ADF (audio digital filter)

Yes

CORDIC co-processor

Yes

FMAC (filter mathematical 
accelerator)

Yes

RTC (real-time clock)

Yes

Tamper pins (without SMPS / 
with SMPS)
Active tampers (without SMPS / 
with SMPS)

(6)

3 / 3

2 / 2

4 / 3

3 / 2

- / 8

- / 7

8 / 7

7 / 6

8 / 8

7 / 7

8 / 7

7 / 6

8 / 8

7 / 7

True random number generator

Yes

HASH (SHA-256)

Yes

GPIOs (without SMPS / 
with SMPS)
Wake-up pins (without SMPS / 
with SMPS)
Number of I/Os down to 1.08 V 
(without SMPS / with SMPS)

37 / 33

17 / 15

0 / 0

51 / 47

18 / 17

0 / 0

69

23

6

82 / 79

23 / 22

0 / 0

110 / 106

24 / 24

13 / 10

114 / 111

24 / 23

14 / 13

136 / 133

24 / 24

14 / 11

Capacitive sensing 
Number of channels (without SMPS 
/ with SMPS)

5 / 4

10 / 9

11

19 / 18

22 / 22

22 / 21

22 / 22

Table 2. STM32U575xx features and peripheral counts (continued)

Peripherals

STM32

U

575

CG/I 

STM32

U

575

RG/I 

STM32U

575

OG/I 

STM3

2U57

5VG/I 

STM32U

575

QG/I 

ST

M3

2U57

5Z

G/I 

STM32

U

575

AG/I 

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Description

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DS13737 Rev 10

ADC

12-bit ADC

1

14-bit ADC

1

Nbr of channels 
(without SMPS / 
with SMPS)

11 / 10

17 / 15

16

20 / 18

24 / 24

24 / 22

24 / 24

DAC

Number of 12-bit 
D-to-A converters

2

Internal voltage reference buffer

No

Yes

Analog comparator

2

Operational amplifiers

2

Maximum CPU frequency

160 MHz

Operating voltage

1.71 to 3.6 V

Operating temperature

Ambient operating temperature: –40 to +85 °C / –40 to +125 °C

Junction temperature: –40 to +105 °C / –40 to +130 °C

Package

LQFP48, 

UFQFPN

48

LQFP64

WLCSP

90

LQFP

100

UFBGA

132

LQFP144

UFBGA

169

1. For the WLCSP90 package, FSMC can only support 8-bit LCD interface.

2. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory 

using the NE1 chip select.

3. Two OCTOSPIs are available only in Muxed mode.

4. When both are used simultaneously, one supports only SDIO interface.

5. Available on packages without SMPS, not available on packages with SMPS.

6. Active tampers in output sharing mode (one output shared by all inputs).

Table 2. STM32U575xx features and peripheral counts (continued)

Peripherals

STM32

U

575

CG/I 

STM32

U

575

RG/I 

STM32U

575

OG/I 

STM3

2U57

5VG/I 

STM32U

575

QG/I 

ST

M3

2U57

5Z

G/I 

STM32

U

575

AG/I 

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Description

21

Figure 1. STM32U575xx block diagram 

MSv67841V4

@V

SW

USB FS

NJTRST, JTDI, JTCK/SWCLK, 

JTMS/SWDIO, JTDO

TRACECLK,

TRACED[3:0]        

CLK, NE[4:1], NL, NBL[1:0],
A[25:0], D[15:0], NOE, NWE,
NWAIT, NCE, INT as AF

JTAG/ SW

MPU

ETM

NVIC

Arm Cortex-M33
160 MHz
TrustZone  FPU

C-BUS

S-BUS

ICACHE

(8 Kbytes)

DCACHE1

(4 Kbytes)

D[7:0], D[3:1]dir

CMD, CMDdir,CK, CKin

D0dir, D2dir

SDMMC1

FIFO

SDMMC2

FIFO

DMA2D

GPDMA1

AHB bus-matrix

TSC

MDF1

GPIO port A

GPIO port B

GPIO port C

GPIO port D

GPIO port E

GPIO port F

GPIO port G

GPIO port H

GPIO port I

EXT IT. WKP

8 groups of 4 channels max 

as AF

SDIN[5:0], CKIN[5:0], CCK0, 

CCK1 as AF                

PA[15:0]

PB[15:0]

PC[15:13]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:2]

PH[15:0]

PI[7:0]

136 AF

17xIN

@V

DDA

ADC1

ITF

3 compl. channels 

(TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

TIM1/PWM      16b

3 compl. channels 

(TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

TIM8/PWM     16b

2 channels,

1 compl. channel, BKIN as AF

TIM15         16b

1 channel,

1 compl. channel, BKIN as AF

TIM16         16b

1 channel,

1 compl. channel, BKIN as AF

TIM17         16b

RX, TX, CK,CTS, RTS as AF

MOSI, MISO, SCK, NSS as 

AF

SPI1

smcard
  irDA                                                                                                                

USART1

MCLK_A, SD_A, FS_A, 

SCK_A, MCLK_B, SD_B, 

FS_B, SCK_B as AF

MCLK_A, SD_A, FS_A, 

SCK_A, MCLK_B, SD_B, 

FS_B, SCK_B as AF

SAI2

SAI1

        

APB2 160 MHz

SYSCFG

AHB/APB2

AHB/APB1

FMAC

CORDIC

CRC

AHB2 160 MHz

AHB1 160 MHz

SRAM3 (512 Kbytes)

SRAM2 (64 Kbytes)

SRAM1 (192 Kbytes)

Flash memory

(up to 2 Mbytes)

Octo-SPI2 memory interface

Octo-SPI1 memory interface

Flexible static memory controller (FSMC):

SRAM, PSRAM, NOR Flash,FRAM, NAND Flash

IO[7:0], CLK, NCLK, NCS. 
DQS as AF

RNG

HASH

PHY

DP
DM

D[15:0], CK, CMD as AF

DCMI/PSSI

@V

DD

Power management

Voltage regulator LDO 

and SMPS

VDD = 1.71 to 3.6 V
VSS

VDD

@V

DD

Supply supervision

BOR

VDDIO, VDDUSB, VDDA, 
VSSA, VDD, VSS, NRST

Reset

PVD, PVM

Int

@V

DD

XTAL OSC 

4- 50 MHz

IWDG

OSC_IN
OSC_OUT

Standby
interface

@V

DD

MSI

HSI16

PLL 1, 2, 3

Reset and clock control

FCLK

HCLKx

PCLKx

APB1 160 MHz (max)

TIM2    32b

TIM3    32b

TIM4    32b

TIM5    32b

smcard

irDA

UART4

UART5

SPI2

I2C1/SMBUS

I2C2/SMBUS

I2C4/SMBUS

FDCAN1

USART2

smcard

irDA

USART3

FIFO

4 channels, ETR as AF

4 channels, ETR as AF

4 channels, ETR as AF

4 channels, ETR as AF

RX, TX, CK, CTS, RTS as AF

RX, TX, CK, CTS, RTS as AF

RX, TX, CTS, RTS as AF         

RX, TX, CTS, RTS as AF

MOSI, MISO, SCK, NSS as 
AF

SCL, SDA, SMBA as AF

SCL, SDA, SMBA as AF

SCL, SDA, SMBA as AF

TX, RX as AF

WWDG

CRS

TIM6  16b

TIM7  16b

UCPD1

CC1, DBCC1, CC2, DBCC2,  
FRSCC1, FRSCC2 as AF        

LPTIM2

IN1, IN2, CH1, CH2, 
ETR as AF

SRAM4

(16 Kbytes)

LPDMA1

@V

DDA

D/A converter 1

ITF

DAC1_OUT1

@V

DDA

ADC4

ITF

DAC1_OUT2

19xIN

AHB3 160 MHz

LPGPIO

IO[15:0] as AF

ADF1

SDIN0, CKIN0, CCK0, 
CCK1 as AF

AHB/APB3

APB3 160 MHz

Temperature 

monitoring

@V

SW

XTAL 32k

RTC

RTC_OUT1, RTC_OUT2, 

RTC_REFIN, RTC_TS

TAMP

TAMP_OUT[8:1], 

TAMP_IN[8:1]

@V

DDA

VREF buffer

VREF+

@V

DDA

COMP1

INP, INN, OUT

COMP2

INP, INN, OUT

@V

DDA

OpAmp1

INP, INN, OUT

OpAmp2

INP, INN, OUT

LPTIM1

IN1, IN2, CH1, CH2, 

ETR as AF

LPTIM3

IN1, IN2, CH1, CH2, 

ETR as AF

LPTIM4

IN1, OUT, ETR as AF

I2C3/SMBUS

SCL, SDA, SMBA as AF

SPI3

MOSI, MISO, SCK, NSS as 

AF

LPUART1

V

DD

power domain

V

DDUSB

power 

domain

V

SW

power 

domain

V

DDIO2

power 

domain

V

DDA 

power 

domain

IO[7:0], CLK, NCLK, NCS. 
DQS as AF

AHB bus-matrix

RX, TX, CTS, RTS_DE as 

AF

FIFO

@V

DDUSB

BKPSRAM 

(2 Kbytes)

PHY

AUDIOCLK as AF

GTZC1

GTZC2

HSI48

WKUPx (x=1 to 8)

Note: V

SW

= V

DD

when V

DD

is above V

BOR0

, and V

SW

= V

BAT

when V

SS

is below V

BOR0

.

PC[12:0]

D/A converter 2

PG[1:0]

@V

SW

LSI

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3 Functional 

overview

3.1 

Arm Cortex-M33 core with TrustZone

 

and FPU

The Cortex-M33 with TrustZone

 

and FPU is a highly energy-efficient processor designed for 

microcontrollers and deeply embedded applications, especially those requiring efficient 
security. 

The Cortex-M33 processor delivers a high computational performance with low-power 
consumption and an advanced response to interrupts. It features:

Arm TrustZone technology, using the Armv8-M main extension supporting secure and 
nonsecure states

MPUs (memory protection units), supporting up to 16 regions for secure and

 

nonsecure applications

Configurable SAU (secure attribute unit) supporting up to eight memory regions as 
secure or nonsecure

Floating-point arithmetic functionality with support for single precision arithmetic

The processor supports a set of DSP instructions that allows an efficient signal processing 
and a complex algorithm execution.

The Cortex-M33 processor supports the following bus interfaces:

System AHB bus: 
The S-AHB (system AHB) bus interface is used for any instruction fetch and data 
access to the memory-mapped SRAM, peripheral, external RAM and external device, 
or Vendor_SYS regions of the Armv8-M memory map.

Code AHB bus:
The C-AHB (code AHB) bus interface is used for any instruction fetch and data access 
to the code region of the Armv8-M memory map.

Figure 1

 shows the general block diagram of the STM32U575xx devices.

3.2 ART 

Accelerator 

(ICACHE and DCACHE)

3.2.1 

Instruction cache (ICACHE)

The ICACHE is introduced on C-AHB code bus of Cortex-M33 processor to improve 
performance when fetching instruction (or data) from both internal and external memories.

ICACHE offers the following features:

Multibus interface:

Slave port receiving the memory requests from the Cortex-M33 C-AHB code 
execution port

Master1 port performing refill requests to internal memories (Flash memory and 
SRAMs)

Master2 port performing refill requests to external memories (external flash 
memory and RAMs through Octo-SPI and FMC interfaces)

Second slave port dedicated to ICACHE registers access

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Close to zero wait-states instructions/data access performance:

0 wait-state on cache hit

Hit-under-miss capability, allowing to serve new processor requests while a line 
refill (due to a previous cache miss) is still ongoing

Critical-word-first refill policy, minimizing processor stalls on cache miss

Hit ratio improved by two-ways set-associative architecture and pLRU-t 
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm 
with best complexity/performance balance

Dual master ports allowing to decouple internal and external memory traffics, on 
fast and slow buses, respectively; also minimizing impact on interrupt latency

Optimal cache line refill thanks to AHB burst transactions (of the cache line size)

Performance monitoring by means of a hit counter and a miss counter

Extension of cacheable region beyond the code memory space, by means of address 
remapping logic that allows four cacheable external regions to be defined

Power consumption reduced intrinsically (more accesses to cache memory rather to 
bigger main memories); even improved by configuring ICACHE as direct mapped 
(rather than the default two-ways set-associative mode)

TrustZone security support

Maintenance operation for software management of cache coherency

Error management: detection of unexpected cacheable write access, with optional 
interrupt raising

3.2.2 

Data cache (DCACHE)

The DCACHE is introduced on S-AHB system bus of Cortex-M33 processor to improve the 
performance of data traffic to/from external memories.

DCACHE offers the following features:

Multibus interface:

Slave port receiving the memory requests from the Cortex-M33 S-AHB system 
port

Master port performing refill requests to external memories (external flash memory 
and RAMs through Octo-SPI and FMC interfaces)

Second slave port dedicated to DCACHE registers access

Close to zero wait-states external data access performance:

Zero wait-states on cache hit

Hit-under-miss capability, allowing to serve new processor requests to cached 
data, while a line refill (due to a previous cache miss) is still ongoing

Critical-word-first refill policy for read transactions, minimizing processor stalls on 
cache miss 

Hit ratio improved by two-ways set-associative architecture and pLRU-t 
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm 
with best complexity/performance balance

Optimal cache line refill thanks to AHB burst transactions (of the cache line size)

Performance monitoring by means of two hit counters (for read and write) and two 
miss counters (for read and write)

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Supported cache accesses:

Both write-back and write-through policies supported (selectable with AHB 
bufferable attribute)

Read and write-back always allocated

Write-through always nonallocated (write-around)

Byte, half-word, and word writes supported

TrustZone security support

Maintenance operations for software management of cache coherency: 

Full cache invalidation (noninterruptible)

Address range clean and/or invalidate operations (background task, interruptible)

Error management: detection of error for master port request initiated by DCACHE (line 
eviction or clean operation), with optional interrupt raising

3.3 

Memory protection unit

The MPU (memory protection unit) is used to manage the CPU accesses to the memory 
and to prevent one task to accidentally corrupt the memory or the resources used by any 
other active task. This memory area is organized into up to 16 protected areas. 
The MPU regions and registers are banked across secure and nonsecure states.

The MPU is especially helpful for applications where some critical or certified code must be 
protected against the misbehavior of other tasks. It is usually managed by an RTOS 
(real-time operating system). 

If a program accesses a memory location that is prohibited by the MPU, the RTOS can 
detect it and take action. In an RTOS environment, the kernel can dynamically update the 
MPU area setting based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.4 

Embedded flash memory

The devices feature up to 2 Mbytes of embedded flash memory that is available for storing 
programs and data. The flash memory supports 10 000 cycles and up to 100 000 cycles 
on 512 Kbytes.

A 128-bit instruction prefetch is implemented and can optionally be enabled.

The flash memory interface features:

Dual-bank operating modes

Read-while-write (RWW)

This allows a read operation to be performed from one bank while an erase or program 
operation is performed to the other bank. The dual-bank boot is also supported. For 2-
MByte devices: each bank contains 128 pages of 8 KBytes. For 1-MByte devices: each 
bank contains 64 pages of 8 KBytes. The flash memory also embeds 512-byte OTP (one-
time programmable) for user data.

The whole nonvolatile memory embeds the ECC (error correction code) feature supporting:

single-error detection and correction

double-error detection

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ECC fail address report

3.4.1 Flash 

memory 

protection

The option bytes allow the configuration of flexible protections:

write protection (WRP) to protect areas against erasing and programming. Two areas 
per bank can be selected with 8-Kbyte granularity.

RDP (readout protection) to protect the whole memory, has four levels of protection 
available (see 

Table 3

 an

Table 4

):

Level 0: no readout protection

Level 0.5: available only when TrustZone is enabled
All read/write operations (if no write protection is set) from/to the nonsecure flash 
memory are possible. The debug access to secure area is prohibited. 
Debug access to nonsecure area remains possible.

Level 1: memory readout protection
The flash memory cannot be read from or written to if either the debug features 
are connected or the boot in RAM or bootloader are selected. If TrustZone is 
enabled, the nonsecure debug is possible and the boot in SRAM is not possible. 
Regressions from Level 1 to lower levels can be protected by password 
authentication.

Level 2: chip readout protection
The debug features, the boot in RAM and the bootloader selection are disabled. 
A secure secret key can be configured in the secure options to allow the 
regression capability from level 2 to level 1. By default (key not configured), this 
level 2 selection is irreversible and JTAG/SWD interfaces are disabled. If the 
secret key was previously configured in lower RDP levels, the device enables the 
RDP regression from level 2 to level 1 after password authentication through 
JTAG/SWD interface.

Note:

In order to reach the best protection level, it is recommended to activate TrustZone and to 
set the RDP Level 2 with password authentication regression enabled. 

          

Table 3. Access status versus protection level and execution modes when TZEN = 0 

Area

RDP 

level 

User execution

(boot from Flash memory)

Debug/boot from RAM/ bootloader

(1)

Read Write Erase Read Write Erase 

Flash main memory

1

Yes

Yes

Yes

No

No

No

(4)

2

Yes

Yes

Yes

N/A

N/A

N/A

System memory 

(2)

1

Yes

No

No

Yes

No

No

2

Yes

No

No

N/A

N/A

N/A

Option bytes

(3)

1

Yes

Yes

(4)

N/A

Yes

Yes

(4)

N/A

2

Yes

No

(5)

N/A

N/A

N/A

N/A

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OTP

1

Yes

Yes

(6)

N/A

Yes

Yes

(6)

N/A

2

Yes

Yes

(6)

N/A

N/A

N/A

N/A

Backup registers

1

Yes

Yes

N/A

No

No

N/A

(7)

2

Yes

Yes

N/A

N/A N/A

N/A

SRAM2/backup 

RAM

1

Yes

Yes

N/A

No

No

N/A

(8)

2

Yes

Yes

N/A

N/A

N/A

N/A

1. When the protection level 2 is active, the debug port, the boot from RAM and the boot from system memory are disabled.

2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.

3. Option bytes are only accessible through the flash memory registers and OPSTRT bit.

4. The flash main memory is erased when the RDP option byte changes from level 1 to level 0.

5. SWAP_BANK option bit can be modified.

6. OTP can only be written once.

7. The backup registers are erased when RDP changes from level 1 to level 0.

8. All SRAMs are erased when RDP changes from level 1 to level 0.

Table 3. Access status versus protection level and execution modes when TZEN = 0 (continued)

Area

RDP 

level 

User execution

(boot from Flash memory)

Debug/boot from RAM/ bootloader

(1)

Read Write Erase Read Write Erase 

Table 4. Access status versus protection level and execution modes when TZEN = 1 

Area

RDP 

level 

User execution

(boot from flash memory)

Debug/ bootloader

(1)

Read Write Erase Read Write Erase 

Flash main memory

0.5

Yes

Yes

Yes

Yes

(2)

 Yes

(2)

Yes

(2)

1

Yes

Yes

Yes

No

No

No

(5)

2

Yes

Yes

Yes

N/A

N/A

N/A

System memory 

(3)

0.5

Yes

No

No

Yes

No

No

1

Yes

No

No

Yes

No

No

2

Yes

No

No

N/A

N/A

N/A

Option bytes

(4)

0.5

Yes

Yes

(5)

N/A

Yes

Yes 

(5)

N/A

1

Yes

Yes

(5)

N/A

Yes

Yes

(5)

N/A

2

Yes

No

(6)

N/A

N/A

N/A

N/A

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3.4.2 

Additional flash memory protections when TrustZone activated

When the TrustZone security is enabled through option bytes, the whole flash memory is 
secure after reset, and the following protections are available:

nonvolatile watermark-based secure flash memory area
The secure area can be accessed only in secure mode. One area per bank can be 
selected with a page granularity.

secure HDP (hide protection area)
It is part of the flash memory secure area and can be protected to deny an access to 
this area by any data read, write and instruction fetch. For example, a software code in 
the secure flash memory hide protection area can be executed only once and deny any 
further access to this area until next system reset. One area per bank can be selected 
at the beginning of the secure area.

volatile block-based secure flash memory area
Each page can be programmed on-the-fly as secure or nonsecure. 

OTP

0.5

Yes

Yes

(7)

N/A

Yes

Yes

(7)

N/A

1

Yes

Yes

(7)

N/A

Yes

Yes

(7)

N/A

2

Yes

Yes

(7)

N/A

N/A

N/A

N/A

Backup registers

0.5

Yes

Yes

N/A

Yes

(2)

Yes

(2)

N/A

(8)

1

Yes

Yes

N/A

No

No

N/A

(8)

2

Yes

Yes

N/A

N/A

N/A

N/A

SRAM2/backup 

RAM

0.5

Yes

Yes

N/A

Yes

(2)

Yes

(2)

N/A

(9)

1

Yes

Yes

N/A

No

No

N/A

(9)

2

Yes

Yes

N/A

N/A

N/A

N/A

1. When the protection level 2 is active, the debug port and the bootloader mode are disabled.

2. Depends on TrustZone security access rights.

3. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.

4. Option bytes are only accessible through the flash memory registers and OPSTRT bit.

5. The flash main memory is erased when the RDP option byte regresses from level 1 to level 0.

6. SWAP_BANK option bit can be modified.

7. OTP can only be written once.

8. The backup registers are erased when RDP changes from level 1 to level 0.

9. All SRAMs are erased when RDP changes from level 1 to level 0.

Table 4. Access status versus protection level and execution modes when TZEN = 1 (continued)

Area

RDP 

level 

User execution

(boot from flash memory)

Debug/ bootloader

(1)

Read Write Erase Read Write Erase 

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3.4.3 FLASH 

privilege 

protection

Each flash memory page can be programmed on-the-fly as privileged or unprivileged. 

3.5 Embedded 

SRAMs

Five SRAMs are embedded in the STM32U575xx devices, each with specific features. 
SRAM1, SRAM2, and SRAM3 are the main SRAMs. SRAM4 is in the SRAM used for 
peripherals LPBAM (low-power background autonomous mode) in Stop 2 mode.

These SRAMs are made of several blocks that can be powered down in Stop mode to 
reduce consumption: 

SRAM1: three 64-Kbyte blocks (total 192 Kbytes) 

SRAM2: 8-Kbyte + 56-Kbyte blocks (total 64 Kbytes) with optional ECC. In addition, 
SRAM2 blocks can be retained in Standby mode. 

SRAM3: eight 64-Kbyte blocks (total 512 Kbytes) with optional ECC. When ECC is 
enabled, 256 Kbytes support ECC and 192 Kbytes of SRAM3 can be accessed 
without ECC.

SRAM4: 16 Kbytes 

BKPSRAM (backup SRAM): 2 Kbytes with optional ECC. The BKPSRAM can be 
retained in all low-power modes and when V

DD

 is off in V

BAT

 mode, but not in 

Shutdown mode. 

3.5.1 

SRAMs TrustZone security

When the TrustZone security is enabled, all SRAMs are secure after reset. 
The SRAM1, SRAM2, SRAM3, SRAM4 can be programmed as secure or nonsecure by 
blocks, using the MPCBB (block-based memory protection controller). 

The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions 
can be programmed as secure or nonsecure with watermark, using the TZSC (TrustZone 
security controller) in the GTZC

 

(global TrustZone controller).

3.5.2 

SRAMs privilege protection

The SRAM1, SRAM2, SRAM3, SRAM4 can be programmed as privileged or unprivileged 
by blocks, using the MPCBB. The granularity of SRAM privilege block based is a page 
of 512 bytes. Backup SRAM regions can be programmed as privileged or unprivileged 
with watermark, using the TZSC (TrustZone security controller) in the GTZC

 

(global 

TrustZone controller).

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3.6 TrustZone 

security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.

When the TrustZone is enabled, the SAU (security attribution unit) and IDAU 
(implementation defined attribution unit) define the access permissions based on secure 
and nonsecure state. 

SAU: up to eight SAU configurable regions are available for security attribution.

IDAU: It provides a first memory partition as nonsecure or nonsecure callable 
attributes. It is then combined with the results from the SAU security attribution and 
the higher security state is selected.

Based on IDAU security attribution, the flash memory, system SRAM, and peripheral 
memory space is aliased twice for secure and nonsecure states. However, the external 
memory space is not aliased.

The table below shows an example of typical SAU region configuration based on IDAU 
regions. The user can split and choose the secure, nonsecure, or NSC regions for external 
memories as needed.

Table 5. Example of memory map security attribution versus SAU configuration regions 

Region 

description

Address range

IDAU security 

attribution

SAU security 

attribution typical 

configuration

Final security 

attribution

Code - external memories

0x0000 0000

0x07FF FFFF

Nonsecure

Secure or

nonsecure or NSC

(1)

Secure or

nonsecure or NSC

Code - Flash and SRAM

0x0800 0000

0x0BFF FFFF

Nonsecure

Nonsecure

Nonsecure

0x0C00 0000

0x0FFF FFFF

NSC

Secure or NSC

Secure or NSC

Code - external memories

0x1000 0000

0x17FF FFFF

Nonsecure

Nonsecure

0x1800 0000

0x1FFF FFFF

SRAM

0x2000 0000

0x2FFF FFFF

Nonsecure

0x3000 0000

0x3FFF FFFF

NSC

Secure or NSC

Secure or NSC

Peripherals

0x4000 0000

0x4FFF FFFF

Nonsecure

Nonsecure

Nonsecure

0x5000 0000

0x5FFF FFFF

NSC

Secure or NSC

Secure or NSC

External memories

0x6000 0000

0xDFFF FFFF

Nonsecure

Secure or

nonsecure or NSC

Secure or

nonsecure or NSC

1. NSC = nonsecure callable.

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3.6.1 TrustZone 

peripheral classification 

When the TrustZone security is active, a peripheral can be either securable or 
TrustZone-aware type as follows: 

securable: peripheral protected by an AHB/APB firewall gate that is controlled from 
TZSC to define security properties 

TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing 
a specific TrustZone behavior such as a subset of registers being secure

3.6.2 

Default TrustZone security state

The default system security state is detailed below:

CPU:

Cortex-M33 is in secure state after reset. The boot address must be in secure 
address.

Memory map:

SAU is fully secure after reset. Consequently, all memory map is fully secure. 
Up to eight SAU configurable regions are available for security attribution.

Flash memory:

Flash memory security area is defined by watermark user options.

Flash memory block based area is nonsecure after reset.

SRAMs:

All SRAMs are secure after reset. MPCBB (memory protection block based 
controller) is secure.   

External memories: 

FSMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection 
watermark based controller) is secure.

Peripherals

Securable peripherals are nonsecure after reset.

TrustZone-aware peripherals are nonsecure after reset. Their secure configuration 
registers are secure.

All GPIOs are secure after reset.

Interrupts:

NVIC: All interrupts are secure after reset. NVIC is banked for secure and 
nonsecure state.

TZIC: All illegal access interrupts are disabled after reset.

3.7 Boot 

modes

At startup, a BOOT0 pin, nBOOT0, NSBOOTADDx[24:0] (x = 0, 1) and 
SECBOOTADD0[24:0] option bytes are used to select the boot memory address that 
includes:

Boot from any address in user flash memory.

Boot from system memory bootloader.

Boot from any address in embedded SRAM.

Boot from RSS (root security services).

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The BOOT0 value comes from the PH3-BOOT0 pin or from an option bit depending on the 
value of a user option bit to free the GPIO pad if needed.

The bootloader is located in the system memory, programmed by ST during production. 
The bootloader is used to reprogram the flash memory by using USART, I2C, SPI, FDCAN, 
or USB FS in device mode through the DFU (device firmware upgrade).

The bootloader is available on all devices. Refer to the application note 

STM32 microcontroller system memory boot mode

 (AN2606) for more details. 

The RSS are embedded in a flash memory area named secure information block, 
programmed during ST production.

For example, the RSS enable the SFI (secure firmware installation), thanks to the RSSe SFI 
(RSS extension firmware).

This feature allows customer to produce the confidentiality of the firmware to be provisioned 
into the STM32, when production is subcontracted to untrusted third party.

The RSS are available on all devices, after enabling the TrustZone through the TZEN option 
bit. Refer to the application note 

Overview secure firmware install

 (SFI) (AN4992) 

for more details.

Refer to 

Table 6

 an

Table 7

 for boot modes when TrustZone is disabled and 

enabled respectively.

          

When TrustZone is enabled by setting the TZEN option bit, the boot space must be in the 
secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure 
memory address.

A unique boot entry option can be selected by setting the BOOT_LOCK option bit, allowing 
to boot always at the address selected by SECBOOTADD0[24:0] option bytes. All other boot 
options are ignored.

Table 6. Boot modes when TrustZone is disabled (TZEN = 0) 

nBOOT0

FLASH_

OPTR[27]

BOOT0 

pin PH3

nSWBOOT0

FLASH_

OPTR[26]

Boot address 

option-byte 

selection

Boot area

ST programmed 

default value

-

0

1

NSBOOTADD0[24:0]

Boot address defined by 

user option bytes 

NSBOOTADD0[24:0]

Flash: 0x0800 0000

-

1

1

NSBOOTADD1[24:0]

Boot address defined by 

user option bytes 

NSBOOTADD1[24:0]

Bootloader: 

0x0BF9 0000

1

-

0

NSBOOTADD0[24:0]

Boot address defined by 

user option bytes 

NSBOOTADD0[24:0]

Flash: 0x0800 0000

0

-

0

NSBOOTADD1[24:0]

Boot address defined by 

user option bytes 

NSBOOTADD1[24:0]

Bootloader: 

0x0BF9 0000

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The boot address option bytes allow any boot memory address to be programmed. 
However, the allowed address space depends on the flash memory RDP level.

If the programmed boot memory address is out of the allowed memory mapped area when 
RDP level is 0.5 or more, the default boot address is forced either in secure flash memory or 
nonsecure flash memory, depending on TrustZone security option as described in the table 
below.

          

Table 7. Boot modes when TrustZone is enabled (TZEN = 1) 

BOOT_

LOCK

nBOOT0

FLASH_

OPTR[27]

BOOT0

pin 

PH3

nSWBOOT0

FLASH_

OPTR[26]

RSS 

com-

mand

Boot address 

option-bytes

selection

Boot area

ST pro-

grammed 

default value

0

-

0

1

0

SECBOOTADD0

[24:0]

Secure boot address 

defined by user

option bytes 

SECBOOTADD0[24:0]

Flash: 
0x0C00 0000

-

1

1

0

N/A

RSS

RSS: 
0x0FF8 0000

1

-

0

0

SECBOOTADD0

[24:0]

Secure boot address 

defined by user

option bytes 

SECBOOTADD0[24:0]

Flash: 
0x0C00 0000

0

-

0

0

N/A

RSS

RSS: 
0x0FF8 0000

-

-

-

0

N/A

RSS

RSS: 
0x0FF8 0000

1

-

-

-

-

SECBOOTADD0

[24:0]

Secure boot address 

defined by user

option bytes 

SECBOOTADD0[24:0]

Flash: 
0x0C00 0000

Table 8. Boot space versus RDP protection 

RDP

TZEN = 1

TZEN = 0

0

Any boot address

Any boot address

0.5

Boot address only in RSS or secure Flash memory:

0x0C00 0000 - 0x0C1F FFFF

Otherwise, forced boot address is 0x0FF8 0000.

N/A

1

Any boot address

2

Boot address only in Flash memory

0x0800 0000 - 0x081F FFFF

Otherwise, forced boot address is 0x0800 0000.

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3.8 Global 

TrustZone controller (GTZC)

GTZC is used to configure TrustZone and privileged attributes within the full system.

The GTZC includes three different subblocks:

TZSC: TrustZone security controller
This subblock defines the secure/privilege state of slave/master peripherals. It also 
controls the nonsecure area size for the watermark memory peripheral controller 
(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about 
the secure status of each securable peripheral, by sharing with RCC and I/O logic. 

TZIC: TrustZone illegal access controller
This subblock gathers all security illegal access events in the system and generates 
a secure interrupt towards NVIC. 

MPCBB: MPCBB: block-based memory protection controller
This subblock controls secure states of all memory blocks (512-byte pages) of the 
associated SRAM. This peripheral aims at configuring the internal RAM in a TrustZone 
system product having segmented SRAM with programmable-security and privileged 
attributes.

The GTZC main features are:

Three independent 32-bit AHB interfaces for TZSC, TZIC, and MPCBB

Secure and nonsecure access supported for privileged/unprivileged part of TZSC

Set of registers to define product security settings: 

Secure/privilege regions for external memories 

Secure/privilege access mode for securable peripherals 

Secure/privilege access mode for securable legacy masters 

3.9 Power 

supply 

management

The PWR (power controller) main features are:

Power supplies and supply domains

Core domain (V

CORE

)

V

DD

 domain

Backup domain (V

BAT

)

Analog domain (V

DDA

)

SMPS power stage (V

DDSMPS

, available only on SMPS packages)

V

DDIO2

 domain

V

DDUSB

 for USB transceiver

System supply voltage regulation

SMPS step-down converter

Voltage regulator (LDO)

Power supply supervision

BOR monitor

PVD  monitor

PVM monitor (V

DDA

, V

DDUSB

, V

DDIO2

)

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Power management

Operating modes

Voltage scaling control

Low-power modes

V

BAT

 battery charging

TrustZone security and privileged protection

3.9.1 

Power supply schemes

The devices require a 1.71 V to 3.6 V V

DD 

operating voltage supply. Several independent 

supplies can be provided for specific peripherals:

V

DD

 = 1.71 V to 3.6 V (functionality guaranteed down to V

BORx

 min value)

V

DD 

is the external power supply for the I/Os, the internal regulator and the system 

analog such as reset, power management and internal clocks. It is provided externally 
through the VDD pins.

V

DDA 

= 1.58 V (COMPs) / 1.6 V (DACs, OPAMPs) / 1.62 V (ADCs) / 

1.8 V (VREFBUF) to 3.6 V
V

DDA 

is the external analog power supply for ADCs, DACs, voltage reference buffer, 

operational amplifiers, and comparators. The V

DDA 

voltage level is independent from 

the V

DD 

voltage and must be connected to VDD or VSS pin (preferably to VDD) when 

these peripherals are not used.

V

DDSMPS

 = 1.71 V to 3.6 V

V

DDSMPS

 is the external power supply for the SMPS step-down converter. It is provided 

externally through VDDSMPS supply pin. It must be connected to the same supply 
VDD pin when the SMPS is used in the application. When the SMPS is not used, it is 
recommended to connect both V

DDSMPS

 and V

LXSMPS

 to GND.

V

LXSMPS

 is the switched SMPS step-down converter output. 

Note:

The SMPS power supply pins are available only on a specific package with SMPS 
step-down converter option.

V

DDUSB

 = 3.0 V to 3.6 V

V

DDUSB

 is the external independent power supply for USB transceivers. V

DDUSB 

voltage level is independent from the V

DD

 voltage and must be connected to VDD or 

VSS pin (preferably to VDD) when the USB is not used.

V

DDIO2

 = 1.08 V to 3.6 V

V

DDIO2

 is the external power supply for 14 I/Os (port G[15:2]). The V

DDIO2

 voltage level 

is independent from the V

DD

 voltage and must be connected to VDD or VSS pin 

(preferably to VDD) when PG[15:2] are not used.

V

BAT 

= 1.65 V to 3.6 V (functionality guaranteed down to V

BOR_VBAT

 min value)

V

BAT

 is the power supply for RTC, TAMP, external and internal clocks 32 kHz 

oscillators, and backup registers (through power switch) when V

DD 

is not present.

V

REF-

, V

REF+

V

REF+

 is the input reference voltage for ADCs and DACs. It is also the output of the 

internal voltage reference buffer when enabled.
V

REF+

 can be grounded when ADC and DAC are not active.

The internal voltage reference buffer supports four outputs:

V

REF+

 around 1.5 V. This requires V

DDA

 

 1.8 V.

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V

REF+

 around 1.8 V. This requires V

DDA

 

 2.1 V.

V

REF+

 around 2.048 V. This requires V

DDA

 

 2.4 V.

V

REF+

 around 2.5 V. This requires V

DDA

 

 2.8 V.

VREF- and VREF+ pins are not available on all packages. When not available, they are 
bonded to VSSA and VDDA, respectively. 
When the VREF+ is double-bonded with VDDA in a package, the internal voltage 
reference buffer is not available and must be kept disabled.
V

REF-

 must always be equal to V

SSA

.

The STM32U575xx devices embed two regulators: one LDO and one SMPS in parallel to 
provide the V

CORE 

supply for digital peripherals, SRAM1, SRAM2, SRAM3, and SRAM4 

and embedded flash memory. The SMPS generates this voltage on VDD11 (two pins), with 
a total external capacitor of 4.7 

μ

F typical. SMPS requires an external coil of 2.2 

μ

H typical. 

The LDO generates this voltage on VCAP pin connected to an external capacitor of 4.7 

μ

typical.

Both regulators can provide four different voltages (voltage scaling) and can operate in 
Stop modes.

It is possible to switch from SMPS to LDO and from LDO to SMPS on-the-fly.

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Figure 2. STM32U575xQ power supply overview (with SMPS)

MSv63604V4

USB transceiver

Core

SRAM1
SRAM2
SRAM3
SRAM4

Digital

peripherals

LSE crystal 32 kHz oscillator

  LSI 32 kHz oscillator
  Backup registers
  RCC_BDCR and PWR_BDCR1 registers
  RTC
  TAMP
  BKPSRAM

V

DDA

 domain

Backup domain

Standby circuitry                                
(Wake-up logic, IWDG)

LDO regulator

Low-voltage detector

I/O ring

V

CORE

 domain

Temperature sensor

Reset block

3 x PLL 
Internal RC oscillators

Flash memory

VDDUSB

VDDIO2

V

DDIO1

I/O ring

PG[15:2]

V

DDIO2

VDDA

VSSA

VSS

VSS

V

DDIO2

 domain

V

DD

 domain

V

CORE

VSS

VDD

VBAT

2x VDD11

SMPS regulator

Voltage regulator

VLXSMPS

VDDSMPS

VSSSMPS

A/D converters

Comparators

D/A converters

Operational amplifiers

Voltage reference buffer

V

SW

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Figure 3. STM32U575xx power supply overview (without SMPS)

In this document, V

DDIOx

 refers to the I/O power supply. V

DDIOx

 can be V

DDIO1

 (which is 

supplied by V

DD

), V

DDIO2

 (independent power supply for PG[15:2]), or V

SW

 (supplying 

PC13, PC14, PC15, and all FT_t I/Os in VBAT mode).

V

SW

 = V

DD

 when V

DD

 is above V

BOR0

, and V

SW

 = V

BAT

 when V

DD

 is below V

BOR0

.

During power-up and power-down phases, the following power sequence requirements 
must be respected:

When V

DD 

is below 1 V, other power supplies (V

DDA

, V

DDIO2

, V

DDUSB

) must remain 

below V

DD

 + 300 mV.

When V

DD

 is above 1 V, all power supplies are independent.

During the power-down phase, V

DD

 can temporarily become lower than other supplies 

only if the energy provided to the MCU remains below 1 mJ. This allows external 
decoupling capacitors to be discharged with different time constants during the 
power-down transient phase.

MSv64350V5

USB transceiver

Core

SRAM1
SRAM2
SRAM3
SRAM4

Digital

peripherals

LSE crystal 32kHz oscillator

  LSI 32 kHz oscillator
  Backup registers
  RCC_BDCR and PWR_BDCR1 registers
  RTC
  TAMP
  BKPSRAM

V

DDA

 domain

Backup domain

Standby circuitry                
(Wake-up logic, IWDG)

Low-voltage detector

LDO regulator

I/O ring

V

CORE

 domain

Temperature sensor

Reset block

3 x PLL 
Internal RC oscillators

Flash memory

VDDUSB

VDDIO2

V

DDIO1

I/O ring

PG[15:2]

V

DDIO2

VDDA

VSSA

VSS

VSS

V

DDIO2

 domain

V

DD

 domain

V

CORE

VSS

VDD

VBAT

VCAP

A/D converters

Comparators

D/A converters

Operational amplifiers

Voltage reference buffer

V

SW

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Figure 4. Power-up /down sequence 

1. V

DDX

 refers to any power supply among V

DDA

, V

DDUSB

, and V

DDIO2

.

3.9.2 

Power supply supervisor

The devices have an integrated ultra-low-power BOR (Brownout reset) active in all modes 
(except for Shutdown mode). The BOR ensures proper operation of the device after power-
on and during power-down. The device remains in reset mode when the monitored supply 
voltage V

DD

 is below a specified threshold, without the need for an external reset circuit.

The lowest BOR level is 1.71 V at power-on, and other higher thresholds can be selected 
through option bytes. The devices feature an embedded PVD (programmable voltage 
detector) that monitors the V

DD

 power supply and compares it to the V

PVD

 threshold. 

An interrupt can be generated when V

DD

 drops below and/or rises above the V

PVD

 

threshold. The interrupt service routine can then generate a warning message and/or put 
the MCU into a safe state. The PVD is enabled by software.

In addition, the devices embed a peripheral voltage monitor that compares the independent 
supply voltages V

DDA

, V

DDUSB, 

and V

DDIO2

 to ensure that the peripheral is in its functional 

supply range.

The devices support dynamic voltage scaling to optimize its power consumption in Run 
mode. The voltage from the main regulator that supplies the logic (V

CORE

) can be adjusted 

according to the system’s maximum operating frequency. 

The main regulator operates in the following ranges:

Range 1 (V

CORE

 = 1.2 V) with CPU and peripherals running at up to 160 MHz 

Range 2 (V

CORE

 = 1.1 V) with CPU and peripherals running at up to 110 MHz

Range 3 (V

CORE

 = 1.0 V) with CPU and peripherals running at up to 55 MHz

Range 4 (V

CORE

 = 0.9 V) with CPU and peripherals running at up to 25 MHz

MSv47490V1

0.3

1

V

BOR0

3.6

Operating mode

Power-on

Power-down

time

V

V

DDX

(1)

V

DD

Invalid supply area

V

DDX

< V

DD

+ 300 mV

V

DDX

independent from V

DD

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3.9.3 Low-power 

modes

The ultra-low-power STM32U575xx devices support seven low-power modes to achieve the 

best compromise between low-power consumption, short startup time, available peripherals 

and available wake-up sources.
The table below details the related low-power modes.

          

Table 9. STM32U575xx mode overview 

Mode

Regulator

(1)

CPU Flash SRAM Clocks

DMA and peripherals

(2)

Wake-up source

Run

 Range 1

Yes

ON

(3)

ON

Any

All

N/A

 Range 2

Range 3

Range 4

All except OTG_FS and UCPD

Sleep

 Range 1

No

ON

ON

(4)

Any

All

Any interrupt or 
event

 Range 2

Range 3

Range 4

All except OTG_FS, and UCPD

Stop 0

 Range 1

No

OFF

ON

(5)

LSE

LSI

(6)

BOR, PVD, PVM,
RTC, TAMP, IWDG,
TEMP (temp. sensor), 
VREFBUF,
ADC4

(7)

,

DAC1 (2 channels)

(8)

,

COMPx (x = 1, 2),
OPAMPx (x = 1, 2),
USARTx (x = 1...5)

(9)

,

LPUART1,
SPIx (x = 1...3)

(10)

,

I2Cx (x = 1...4)

(11)

,

LPTIMx (x = 1...4)

(12)

,

MDF1

(13)

, ADF1,

GPIO, LPGPIO,
GPDMA1

(14)

, LPDMA1

All other peripherals are frozen.

Reset pin, all I/Os,
BOR, PVD, PVM, 
RTC, TAMP, IWDG,
TEMP,
ADC4,
DAC1 (2 channels),
COMPx (x = 1, 2),
USARTx (x = 1...5),
LPUART1,
SPIx (x = 1...3),
I2Cx (x = 1...4),
LPTIMx (x = 1...4),
MDF1, ADF1,
GPDMA1, 
LPDMA1,
OTG_FS, UCPD

 Range 2

Range 3

Range 4

Stop 1

LPR

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Stop 2

LPR

No

OFF

ON

(5)

LSE

LSI

BOR, PVD, PVM,
RTC, TAMP, IWDG, 
TEMP, VREFBUF,
ADC4,
DAC1 (2 channels),
COMPx (x = 1, 2),
OPAMPx (x = 1, 2),
LPUART1,
SPI3,
I2C3,
LPTIMx (x = 1, 3, 4),
ADF1,
LPGPIO,
LPDMA1

All other peripherals are frozen.

Reset pin, all I/Os,
BOR, PVD, PVM, 
RTC, TAMP, IWDG,
TEMP,
ADC4,
COMPx (x = 1, 2),
LPUART1,
SPI3,
I2C3,
LPTIMx (x = 1,3,4),
ADF1,
LPDMA1

Stop 3

LPR

No

OFF

ON

(5)

LSE

LSI

BOR,
RTC, TAMP, IWDG, 
DAC1 (2 static channels), 
OPAMPx (x = 1, 2)

All other peripherals are frozen.

I/O configuration can be floating, 
pull-up or pull-down. 

Reset pin,
24 I/Os (WKUPx),
BOR, RTC, TAMP, 
IWDG

Standby

LPR

Po

wered of

f

OFF

6

4-, 56

- o

8-Kbyte 

SRAM2

2-

Kbyte BKPSRAM

(5

)

all

 o

the

r SRAMs 

powe

re

of

f

LSE

LSI

BOR, RTC, TAMP, IWDG

All other peripherals are 
powered off.

I/O configuration can be floating, 
pull-up or pull-down.

Reset pin, 
24 I/Os (WKUPx),
BOR, RTC, TAMP, 
IWDG

OFF

Powered

of

f

Shutdown

OFF

Powe

re

d of

f

OFF

Powered

of

f

LSE

RTC, TAMP

All other peripherals are 
powered off.

I/O configuration can be floating, 
pull-up or pull-down

(15)

.

Reset pin, 
24 I/Os (WKUPx),
RTC, TAMP

 

Table 9. STM32U575xx mode overview (continued)

Mode

Regulator

(1)

CPU Flash SRAM Clocks

DMA and peripherals

(2)

Wake-up source

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Functional overview

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By default, the microcontroller is in Run mode after a system or a power reset. It is up to the 
user to select one of the low-power modes described below:

Sleep

 mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can 
wake up the CPU when an interrupt/event occurs.

Stop 0, Stop 1, Stop 2, and Stop 3 

modes

Stop mode achieves the lowest power consumption while retaining the content of 
SRAM and registers. The SRAMs can be totally or partially switched off to further 
reduce consumption. All clocks in the V

CORE

 domain are stopped, the PLL, the MSI, 

the HSI16, the HSI48, and the HSE crystal oscillators are disabled. The LSE or LSI is 
still running. 
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals are autonomous and can operate in Stop mode by requesting their 
kernel clock and their bus (APB or AHB) when needed, in order to transfer data with 
DMA (GPDMA1 in Stop 0 and Stop 1 modes, LPDMA1 in Stop 0, Stop 1 and Stop 2 
modes). Refer to 

Low-power background autonomous mode (LPBAM)

 for more details. 

LPBAM is not supported in Stop 3 mode.
In Stop 2 and Stop 3 modes, most of the V

CORE

 domain is put in a lower leakage mode. 

Stop 0 and Stop 1 modes offer the largest number of active peripherals and wake-up 
sources, a smaller wake-up time but a higher consumption than Stop 2 mode. 
In Stop 0 mode, the main regulator remains ON, allowing a very fast wake-up time but 
with much higher consumption. 
Stop 3 is the lowest power mode with full retention, but the functional peripherals and 
sources of wake-up are reduced to the same ones than in Standby mode.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 mode can be either MSI 
up to 24 MHz or HSI16, depending on software configuration. 

1. LPR means that the main regulator is OFF and the low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. The flash memory can be put in power-down and its clock can be gated off when executing from SRAM. One bank can 

also be put in power-down mode.

4. The SRAM1, SRAM2, SRAM3, SRAM4, and BKPSRAM clocks can be gated on or off independently.

5. The SRAM can be individually powered off to save power consumption.

6. MSI and HSI16 can be temporary enabled upon peripheral request, for autonomous functions with DMA or wake-up from 

Stop event detections.

7. The ADC4 conversion is functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on 

conversion events.

8. DAC1 is the digital-to-analog (D/A) converter controller instance name. This instance controls two D/A converters also 

called "two channels". The DAC conversions are functional and autonomous with DMA in Stop mode.

9. U(S)ART and LPUART transmission and reception is functional and autonomous with DMA in Stop mode, and can 

generate a wake-up interrupt on transfer events. 

10. SPI transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wake-up 

interrupt on transfer events.

11. I2C transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wake-up 

interrupt on transfer events. 

12. LPTIM is functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on all events. 

13. MDF and ADF are functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on events.

14. GPDMA and LPDMA are functional and autonomous in Stop mode, and can generate a wake-up interrupt on events.

15. I/Os can be configured with internal pull-up, pull-down, or floating in Shutdown mode but the configuration is lost when 

exiting the Shutdown mode.

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DS13737 Rev 10

Standby

 mode

The Standby mode is used to achieve the lowest power consumption with BOR. The 
internal regulator is switched off so that the V

CORE 

domain is powered off. The PLL, the 

MSI, the HSI16, the HSI48, and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The BOR always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O with 
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAMs and register contents are lost except for registers 
and backup SRAM in the backup domain and Standby circuitry. Optionally, the full 
SRAM2 or 8 Kbytes or 56 Kbytes can be retained in Standby mode, supplied by the 
low-power regulator (Standby with SRAM2 retention mode).
The BOR can be configured in ultra-low-power mode to further reduce power 
consumption during Standby mode. 
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, 
WKUP pin event (configurable rising or falling edge), an RTC event occurs (alarm, 
periodic wake-up, timestamp), or a tamper detection. The tamper detection can be 
raised either due to external pins or due to an internal failure detection.
The system clock after wake-up is MSI up to 4 MHz.

Shutdown

 mode

The lowest power consumption is achieved in Shutdown mode. The internal regulator 
is switched off so that the V

CORE

 domain is powered off. The PLL, the HSI16, 

the HSI48, the MSI, the LSI, and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

 

The BOR is not available in Shutdown mode. No power voltage monitoring is possible 
in this mode, therefore the switch to backup domain is not supported (V

BAT 

mode is not 

supported). 
SRAMs and register contents are lost except for registers in the backup domain as long 
as VDD is present. 
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin 
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic 
wake-up, timestamp), or a tamper detection. 
The system clock after wake-up is MSI at 4 MHz.

Low-power background autonomous mode (LPBAM)

The ultra-low-power STM32U575xx devices support LPBAM (low-power background 
autonomous mode) that allows peripherals to be functional and autonomous in Stop mode 
(Stop 0, Stop 1 and Stop 2 modes), so without any software running. 

In Stop 0 and Stop 1 modes, the autonomous peripherals are the following: ADC4, DAC1, 
LPTIMx (x = 1 to 4), USARTx (x = 1 to 5), LPUART1, SPIx (x = 1 to 3), I2Cx (x = 1 to 4), 
MDF1, ADF1, GPDMA1, and LPDMA1. In these modes, SRAM1, SRAM2, SRAM3 and 
SRAM4 can be accessed by the GPDMA1, and SRAM4 can be accessed by the LPDMA1.

In Stop 2 mode, the autonomous peripherals are the following: ADC4, DAC1, LPTIM1, 
LPTIM3, LPTIM4, LPUART1, SPI3, I2C3, ADF1, and LPDMA1. In this mode, the SRAM4 
can be accessed by the LPDMA1.

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Functional overview

90

Those peripherals support the features detailed below:

Functionality in Stop mode thanks to its own independent clock (named kernel clock) 
request capability: the peripheral kernel clock is automatically switched on when 
requested by a peripheral, and automatically switched off when no peripheral 
requests it.

DMA transfers supported in Stop mode thanks to system clock request capability: the 
system clock (MSI or HSI16) automatically switched on when requested by 
a peripheral, and automatically switched off when no peripheral requests it. When the 
system clock is requested by an autonomous peripheral, the system clock is woken up 
and distributed to all peripherals enabled in the RCC. This allows the DMA to access 
the enabled SRAM, and any enabled peripheral register (for instance GPIO or LPGPIO 
registers).

Automatic start of the peripheral thanks to hardware synchronous or asynchronous 
triggers (such as I/Os edge detection and low-power timer event).

Wake-up from Stop mode with peripheral interrupt.

The GPDMA and LPDMA are fully functional and the linked-list is updated in Stop mode, 
allowing the different DMA transfers to be linked without any CPU wake-up. This can be 
used to chain different peripherals transfers, or to write peripherals registers in order to 
change their configuration while remaining in Stop mode. 

The DMA transfers from memory to memory can be started by hardware synchronous or 
asynchronous triggers, and the DMA transfers between peripherals and memories can also 
be gated by those triggers.

Here below some use-cases that can be done while remaining in Stop mode:

A/D or D/A conversion triggered by a low-power timer (or any other trigger)

wake-up from Stop mode on analog watchdog if the A/D conversion result is out of 
programmed thresholds

wake-up from Stop mode on DMA buffer event

Audio digital filter data transfer into SRAM 

wake-up from Stop on sound-activity detection

I

2

C slave reception or transmission, SPI reception, UART/LPUART reception

wake-up at the end of peripheral transfer or on DMA buffer event

I

2

C master transfer, SPI transmission, UART/LPUART transmission, triggered by 

a low-power timer (or any other trigger):

example: sensor periodic read 

wake-up at the end of peripheral transfer or on DMA buffer event

Bridges between peripherals

example: ADC converted data transferred by communication peripherals

Data transfer from/to GPIO/LPGPIO to/from SRAM for:

controlling external components

implementing data transmission and reception protocols

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DS13737 Rev 10

          

Table 10. Functionalities depending on the working mode

(1)

 

Peripheral

Run

Sleep

Stop 0/1

Stop 2

Stop 3

Standby Shutdown

V

BAT

-

W

ake

-u

p

cap

ab

ility

-

W

ake

-u

p

cap

ab

ility

-

W

ake

-u

p

cap

ab

ility

-

W

ake

-u

p

cap

ab

ility

-

W

ake

-u

p

cap

ab

ility

CPU

Y

-

-

-

-

-

-

-

-

-

-

-

-

Flash memory 
(2 Mbytes)

O

(2)

O

(2)

-

-

-

-

-

-

-

-

-

-

-

SRAM1 (192 Kbytes) 

Y

(3)(4)

Y

(3)(4)

O

(7)

-

O

(7)

-

O

(7)

-

-

-

-

-

-

SRAM2 (64 Kbytes)

Y

(3)(4)

Y

(3)(4)

O

(7)

O

(5)

O

(7)

-

O

(7)

-

O

(6)

-

-

-

-

SRAM3 (512 Kbytes)

Y

(3)(4)

Y

(3)(4)

O

(7)

O

(5)

O

(7)

-

O

(7)

-

-

-

-

-

-

SRAM4 (16 Kbytes)

Y

(3)(4)

Y

(3)(4)

O

(7)

-

O

(7)

-

O

(7)

-

-

-

-

-

-

BKPSRAM

O

(4)

O

(4)

O

O

(5)

O

O

O

-

O

FSMC

O

O

-

-

-

-

-

-

-

-

-

-

-

OCTOSPIx (x = 1,2)

O

O

-

-

-

-

-

-

-

-

-

-

-

Backup registers

Y

Y

Y

-

Y

-

Y

-

Y

-

Y

-

Y

BOR (Brownout reset)

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

-

-

-

PVD (programmable 
voltage detector) 

O

O

O

O

O

O

-

-

-

-

-

-

-

Peripheral voltage 
monitor 

O

O

O

O

O

O

-

-

-

-

-

-

-

GPDMA1

O

O

O

O

(8)

-

-

-

-

-

-

-

-

-

LPDMA1

O

O

O

O

(9)

O

O

(9)

-

-

-

-

-

-

-

DMA2D

O

O

HSI16 (high-speed 
internal)

O

O

(10)

-

(10)

-

-

-

-

-

-

-

-

HSI48 oscillator 

O

O

-

-

-

-

-

-

-

-

-

-

-

HSE (high-speed 
external)

O

O

-

-

-

-

-

-

-

-

-

-

-

LSI (low-speed 
internal)

O

O

O

-

O

-

O

-

O

-

-

-

O

LSE (low-speed 
external)

O

O

O

-

O

-

O

-

O

-

O

-

O

MSIS and MSIK 
(multi-speed internal)

O

O

(10)

-

(10)

-

-

-

-

-

-

-

-

CSS (clock security 
system)

O

O

-

-

-

-

-

-

-

-

-

-

-

Clock security system 
on LSE

O

O

O

O

O

O

O

O

O

O

O

O

O

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Functional overview

90

Backup domain 
voltage and 
temperature 
monitoring

O

O

O

O

O

O

O

O

O

O

-

-

O

RTC/TAMP

O

O

O

O

O

O

O

O

O

O

O

O

O

Number of RTC 
tamper pins

8

8

8

O

8

O

8

O

8

O

8

O

8

OTG_FS, UCPD

O

(11)

O

(11)

-

O

-

-

-

-

-

-

-

-

-

USARTx 
(x = 1,2,3,4,5)

O

O

O

(12)

O

(12)

-

-

-

-

-

-

-

-

-

Low-power UART 
(LPUART1)

O

O

O

(12)

O

(12)

O

(12)

O

(12)

-

-

-

-

-

-

-

I2Cx (x = 1,2,4)

O

O

O

(13)

O

(13)

-

-

-

-

-

-

-

-

-

I2C3

O

O

O

(13)

O

(13)

O

(13)

O

(13)

-

-

-

-

-

-

-

SPIx (x = 1,2)

O

O

O

(14)

O

(14)

-

-

-

-

-

-

-

-

-

SPI3

O

O

O

(14)

O

(14)

O

(14)

O

(14)

FDCAN1

O

O

-

-

-

-

-

-

-

-

-

-

-

SDMMCx (x = 1,2)

O

O

-

-

-

-

-

-

-

-

-

-

-

SAIx (x = 1,2)

O

O

-

-

-

-

-

-

-

-

-

-

-

ADC1

O

O

-

-

-

-

-

-

-

-

-

-

-

ADC4

O

O

O

(15)

O

(15)

O

(15)

O

(15)

-

-

-

-

-

-

-

DAC1 (2 converters)

O

O

O

-

O

-

-

-

-

-

-

-

-

VREFBUF

O

O

O

-

O

-

-

-

-

-

-

-

-

OPAMPx (x = 1,2)

O

O

O

-

O

-

-

-

-

-

-

-

-

COMPx (x = 1,2)

O

O

O

O

O

O

-

-

-

-

-

-

-

Temperature sensor

O

O

O

-

O

-

-

-

-

-

-

-

-

Timers (TIMx)

O

O

-

-

-

-

-

-

-

-

-

-

-

LPTIMx (x = 1,3,4)

O

O

O

(16)

O

(16)

O

(16)

O

(16)

-

-

-

-

-

-

-

LPTIM2

O

O

O

(16)

O

(16)

-

-

-

-

-

-

-

-

-

IWDG (independent 
watchdog)

O

O

O

O

O

O

O

O

(17)

O

(17)

-

-

-

WWDG (window 
watchdog)

O

O

-

-

-

-

-

-

-

-

-

-

-

Table 10. Functionalities depending on the working mode

(1)

 (continued)

Peripheral

Run

Sleep

Stop 0/1

Stop 2

Stop 3

Standby Shutdown

V

BAT

-

Wa

k

e-

u

p

ca

pab

ility

-

Wa

k

e-

u

p

ca

pab

ility

-

Wa

k

e-

u

p

ca

pab

ility

-

Wa

k

e-

u

p

ca

pab

ility

-

Wa

k

e-

u

p

ca

pab

ility

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DS13737 Rev 10

SysTick timer

O

O

-

-

-

-

-

-

-

-

-

-

-

MDF1 (multi-function 
digital filter)

O

O

O

(18)

O

(18)

-

-

-

-

-

-

-

-

-

ADF1 (audio digital 
filter)

O

O

O

(18)

O

(18)

O

(18)

O

(18)

-

-

-

-

-

-

-

DCMI (digital camera 
interface)

O

O

-

-

-

-

-

-

-

-

-

-

-

PSSI (paral. synch. 
slave interface)

O

O

-

-

-

-

-

-

-

-

-

-

-

CORDIC coprocessor

O

O

-

-

-

-

-

-

-

-

-

-

-

FMAC (filter 
mathematical 
accelerator)

O

O

-

-

-

-

-

-

-

-

-

-

-

TSC (touch sensing 
controller)

O

O

-

-

-

-

-

-

-

-

-

-

-

RNG (true random 
number generator)

O

O

-

-

-

-

-

-

-

-

-

-

-

HASH accelerator

O

O

-

-

-

-

-

-

-

-

-

-

-

CRC calculation unit

O

O

-

-

-

-

-

-

-

-

-

-

-

GPIOs

O

O

O

O

O

O

-

(19)

24 

pins

-

(19)

24 

pins

-

(20)

24 

pins

-

1. Y = yes (enabled). O = optional (disabled by default, can be enabled by software). - = not available.

 

Gray cells highlight the wake-up capability in each mode.

2. The flash memory can be configured in power-down mode. By default, it is not in power-down mode.

3. The SRAMs can be powered on or off independently.

4. The SRAM clock can be gated on or off independently. 

5. ECC error interrupt or NMI wake-up from Stop mode.

6. 8-Kbyte, 56-Kbyte or full SRAM2 content can be preserved.

7. Subblocks or full SRAM1 and SRAM3, full SRAM2, and SRAM4 can be powered-off to save power consumption. SRAM1, 

SRAM2, SRAM3 and SRAM4 can be accessed by GPDMA1 in Stop 0 and Stop 1 modes. SRAM4 can be accessed by 

LPDMA1 in Stop 0, Stop 1 and Stop 2 modes.

8. GPDMA transfers are functional and autonomous in Stop mode, and generates a wake-up interrupt on transfer events.

9. LPDMA transfers are functional and autonomous in Stop mode, and generates a wake-up interrupt on transfer events.

10. Some peripherals with autonomous mode and wake-up from Stop capability can request HSI16, MSIS, or MSIK to be 

enabled. In this case, the oscillator is woken up by the peripheral, and is automatically put off when no peripheral needs it.

11. OTG_FS is functional in voltage scaling range 1, 2, and 3.

12. USART and LPUART reception and transmission are functional and autonomous in Stop mode in asynchronous and 

in SPI master modes, and generate a wake-up interrupt on transfer events.

13. I

2

C reception and transmission are functional and autonomous in Stop mode, and generate a wake-up interrupt 

on transfer events.

Table 10. Functionalities depending on the working mode

(1)

 (continued)

Peripheral

Run

Sleep

Stop 0/1

Stop 2

Stop 3

Standby Shutdown

V

BAT

-

Wa

k

e-

u

p

ca

pab

ility

-

Wa

k

e-

u

p

ca

pab

ility

-

Wa

k

e-

u

p

ca

pab

ility

-

Wa

k

e-

u

p

ca

pab

ility

-

Wa

k

e-

u

p

ca

pab

ility

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STM32U575xx

Functional overview

90

3.9.4 Reset 

mode 

In order to improve the consumption under reset, the I/O state under and after reset is 
“analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is 
deactivated when the reset source is internal.

3.9.5 VBAT 

operation

The VBAT pin allows the device V

BAT

 domain to be powered from an external battery or 

an external supercapacitor. 

The VBAT pin supplies the RTC with LSE, antitamper detection (TAMP), backup registers, 
and 2-Kbyte backup SRAM. Eight antitamper detection pins are available in V

BAT

 mode.

The VBAT operation is automatically activated when V

DD

 is not present. An internal 

V

BAT 

battery charging circuit is embedded and can be activated when V

DD

 is present.

Note:

When the microcontroller is supplied from V

BAT

, neither external interrupts nor RTC/TAMP 

alarm/events exit the microcontroller from the V

BAT

 operation.

3.9.6 

PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in 
TrustZone security mode. 

The PWR TrustZone security secures the following configuration:

low-power mode

WKUP (wake-up) pins

voltage detection and monitoring

V

BAT

 mode

Some of the PWR configuration bits security is defined by the security of other peripherals:

The VOS (voltage scaling) configuration is secure when the system clock selection is 
secure in RCC. 

The I/O pull-up/pull-down in Standby mode configuration is secure when the 
corresponding GPIO is secure.

3.10 

Peripheral interconnect matrix

Several peripherals have direct connections between them, that allow autonomous 
communication between them and support the saving of CPU resources (thus power supply 
consumption). In addition, these hardware connections allow fast and predictable latency.

14. SPI reception and transmission are functional and autonomous in Stop mode, and generate a wake-up interrupt 

on transfer events.

15. A/D conversion is functional and autonomous in Stop mode, and generates a wake-up interrupt on conversion events.

16. LPTIM is functional and autonomous in Stop mode, and generates a wake-up interrupt on events.

17. Only IWDG reset can exit the device from Stop 3 and Standby modes. Wake-up with IWDG interrupt is not supported.

18. MDF and ADF are functional and autonomous in Stop mode, and generate a wake-up interrupt on events.

19. I/Os can be configured with internal pull-up, pull-down, or floating in Stop 3 and Standby modes.

20. I/Os can be configured with internal pull-up, pull-down, or floating in Shutdown mode but the configuration is lost when 

exiting the Shutdown mode.

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Depending on the peripherals, these interconnections can operate in Run, Sleep, Stop 0, 
Stop 1, and Stop 2 modes. 

3.11 

Reset and clock controller (RCC)

The RCC (reset and clock control) manages the different reset types, and generates all 
clocks for the bus and peripherals.

The RCC distributes the clocks coming from the different oscillators to the core and to 
the peripherals. It also manages the clock gating for low-power modes and ensures the 
clock robustness. It features:

Clock prescaler: in order to get the best trade-off between speed and current 
consumption, the clock frequency to the CPU and peripherals can be adjusted by 
a programmable prescaler.

Clock security system: clock sources can be changed safely on-the-fly in Run mode 
through a configuration register.

Clock management: in order to reduce the power consumption, the clock controller 
can stop the clock to the core, individual peripherals or memory.

System clock source: four different clock sources can be used to drive the master 
clock SYSCLK:

HSE (4 to 50 MHz high-speed external crystal or ceramic resonator) that can 
supply a PLL. The HSE can also be configured in bypass mode for an external 
clock.

HSI16 (16 MHz high-speed internal RC oscillator) trimmable by software that can 
supply a PLL.

MSI (multispeed internal RC oscillator) trimmable by software that can generate 
16 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is 
available in the system (LSE), the MSI frequency can be automatically trimmed by 
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the 
USB device, saving the need of an external high-speed crystal (HSE). The MSI 
can supply a PLL.

System PLL that can be fed by HSE, HSI16, or MSI, with a maximum frequency 
at 160 MHz.

HSI48 (RC48 with clock recovery system) internal 48 MHz clock source that can be 
used to drive the USB, the SDMMC, or the RNG peripherals. This clock can be output 
on the MCO.

UCPD kernel clock, derived from HSI16 clock. The HSI16 RC oscillator must be 
enabled prior to the UCPD kernel clock use.

Auxiliary clock source: two ultra-low-power clock sources that can be used to drive 
the real-time clock:

LSE (32.768 kHz low-speed external crystal), supporting three drive capability 
modes. The LSE can also be configured in bypass mode for an external clock.

LSI (32 kHz low-speed internal RC), also used to drive the independent watchdog. 
The LSI clock accuracy is ±5% accuracy. The LSI clock can be divided by 128 to 
output a 250 Hz as source clock.

Peripheral clock sources: several peripherals have their own independent clock 
whatever the system clock. Three PLLs, each having three independent outputs 

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allowing the highest flexibility, can generate independent clocks for the ADC, USB, 
SDMMC, RNG, MDF, ADF, FDCAN1, OCTOSPIs, and SAIs. 

Startup clock: after reset, the microcontroller restarts by default with MSI. The prescaler 
ratio and clock source can be changed by the application program as soon as the code 
execution starts.

CSS (clock security system): this feature can be enabled by software. If an HSE clock 
failure occurs, the master clock automatically switches to HSI16 and a software 
interrupt is generated if enabled. LSE failure can also be detected and generates 
an interrupt.

Clock-out capability: 

MCO (microcontroller clock output): it outputs one of the internal clocks for 
external use by the application.

LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes 
(except V

BAT

 mode).

Several prescalers allow AHB and APB frequencies configuration. The maximum frequency 
of the AHB and the APB clock domains is 160 MHz.

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Figure 5. Clock tree 

MSv67842V2

SYSCLK

MCO

LSCO

48 MHz clock to OTG_FS

To ADC1, ADC4 and  DAC1

To IWDG

To RTC

HCLK

To AHB bus, core, memory and DMA

FCLK Cortex free running clock

To Cortex system timer

To APB1 peripherals

To APB2 peripherals

PCLK1

PCLK2

LSE

HSI16

To USARTx

(x = 2 to 5)

To I2Cx

(X = 1,2,4)

To LPTIM2

AUDIOCLK

To TIMx

(x = 2 to 7)

OSC32_OUT

OSC32_IN

MSIS
HSI16
HSE

HSE

HSI16

/32

AHB 

PRESC

/ 1,2,..512

/ 8

APB1 

PRESC

/ 1,2,4,8,16

x1 or x2

HSI16

LSI

LSE

HSI16

APB2 

PRESC

/ 1,2,4,8,16

To TIMx

(x = 1,8,15,16,17)

x1 or x2

To USART1

LSE

HSI16

SYSCLK

/ M

HSI RC 16 MHz

HSE OSC

4-50 MHz

Clock 

detector

OSC_OUT

OSC_IN

ĺ

LSI RC

32 kHz or 250 Hz

HSI16

LSI

LSE

HSE
SYSCLK

HSI48

MSIS

To OCTOSPIx

(X = 1,2)

To SDMMCx

(X = 1,2)    

/ M

HSI48 RC 48 MHz

CRS clock

To UCPD1

HSI16

ICLK

LSE OSC

32.768 kHz

Clock 

detector

MSIS 100 kHz – 48 MHz

MSIK 100 kHz – 48 MHz

MSI RC

MSIK

HSI16

To SPI2

LSE

LSI

x4

x3

MSIK

HSE

pll1_q_ck
pll2_p_ck

To FDCAN1

MSIS

MSIK

pll1_r_ck

HSI48

pll1_p_ck

MSIK

LSI

MSIS
HSI16
HSE

PLL3

/ M

pll3_p_ck

pll3_q_ck

pll3_r_ck

MSIS
HSI16
HSE

SYSCLK

MSIK

pll1_q_ck

MSIK

HSI16

SYSCLK

To SPI1

pll1_p_ck
pll2_p_ck
pll3_p_ck

HSI16

To SAIx

(X = 1,2)

x2

pll1_p_ck
pll3_q_ck

MSIK

To ADF1 and MDF1

/ 2

HSI16

To RNG        

x2

HSI48

MSIK

pll1_q_ck
pll2_q_ck

To APB3 peripherals

PCLK3

APB3 

PRESC

/ 1,2,4,8,16

pll2_r_ck

HSE

HSI16

MSIK

x2

LSI

LSE

DAC1 sample and hold clock

SYSCLK

SYSCLK

SYSCLK

LSE

To SPI3

To I2C3

To LPUART1

HSI16

MSIK

HSI16

MSIK

HSI16

MSIK

MSIK

HSI16

LSI

LSE

To LPTIM1, LPTIM3, LPTIM4

Clock 

source 
control

/ Q

/ P

/ R

VCO

/ N

PLL2

/ Q

/ P

/ R

VCO

/ N

pll2_p_ck

pll2_q_ck

pll2_r_ck

PLL1

/ Q

/ P

/ R

VCO

/ N

pll1_p_ck

pll1_q_ck

pll1_r_ck

pll2_q_ck

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3.11.1 RCC 

TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in 
TrustZone security mode. 

The RCC TrustZone security secures some RCC system configuration and peripheral 
configuration clock from being read or modified by nonsecure accesses: when a peripheral 
is secure, the related peripheral clock, reset, clock source selection and clock enable during 
low-power modes control bits are secure.

A peripheral is in secure state:

when its corresponding SEC security bit is set in the TZSC (TrustZone security 
controller), for securable peripherals.

when a security feature of this peripheral is enabled through its dedicated bits, for 
TrustZone-aware peripherals.

3.12 Clock 

recovery system (CRS) 

The devices embed a special block that allows automatic trimming of the internal 48 MHz 
oscillator to guarantee its optimal accuracy over the whole device operational range. This 
automatic trimming is based on the external synchronization signal that is either derived 
from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin 
or generated by user software. For faster lock-in during startup, automatic trimming and 
manual trimming action can be combined.

3.13 General-purpose 

inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), 
as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the 
GPIO pins are shared with digital or analog alternate functions. 

After reset, all GPIOs are in analog mode to reduce power consumption.

The I/Os alternate function configuration can be locked if needed following a specific 
sequence in order to avoid spurious writing to the I/Os registers.

3.13.1 

GPIOs TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O 
pin is configured as secure, its corresponding configuration bits for alternate function, mode 
selection, I/O data are secure against a nonsecure access. The associated registers bit 
access is restricted to a secure software only. After reset, all GPIO ports are secure. 

3.14 Low-power 

general-purpose inputs/outputs (LPGPIO)

The LPGPIO allows dynamic I/O control in Stop 2 mode thanks to LPDMA1. Up to 16 I/Os 
can be configured and controlled as input or output (open-drain or push-pull depending on 
GPIO configuration).

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3.14.1 

LPGPIO TrustZone security 

Each I/O pin registers bit of the LPGPIO is configured as secure if the corresponding I/O is 
configured as secure in the GPIO.

3.15 Multi-AHB 

bus 

matrix

A 32-bit multi-AHB bus matrix interconnects all master (CPU, DMA2D, GPDMA1, SDMMC1, 
SDMMC2) and slave (Flash memory, RAM, FMC, OCTOSPIs, SRAMs, AHB, and APB) 
peripherals. It also ensures a seamless and efficient operation even when several high-
speed peripherals work simultaneously.

Another multi-AHB bus matrix interconnects two masters (previous AHB bus matrix slave 
port and LPDMA1) and all slaves that are functional in Stop 2 modes (SRAM4 and 
AHB/APB peripherals functional in Stop 2 mode).

3.16 System 

configuration controller (SYSCFG) 

The STM32U575xx devices feature a set of configuration registers. The main purposes of 
the system configuration controller are the following:

Managing robustness feature

Configuring FPU interrupts

Enabling/disabling the FMP high-drive mode of some I/Os and voltage booster for I/Os 
analog switches

Managing the I/O compensation cell

Configuring register security access

3.17 

General purpose direct memory access controller (GPDMA)

The general purpose direct memory access (GPDMA) controller is a bus master and system 
peripheral. 

The GPDMA is used to perform programmable data transfers between memory-mapped 
peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.

The GPDMA main features are:

Dual bidirectional AHB master

Memory-mapped data transfers from a source to a destination:

Peripheral-to-memory

Memory-to-peripheral

Memory-to-memory

Peripheral-to-peripheral

Autonomous data transfers during Sleep and Stop modes

Transfers arbitration based on a four-grade programmed priority at a channel level:

One high-priority traffic class, for time-sensitive channels (queue 3)

Three low-priority traffic classes, with a weighted round-robin allocation for non 
time-sensitive channels (queues 0, 1, 2)

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Per channel event generation, on any of the following events: transfer complete or half 
transfer complete or data transfer error or user setting error, and/or update linked-list 
item error or completed suspension

Per channel interrupt generation, with separately programmed interrupt enable 
per event

16 concurrent DMA channels:

Per channel FIFO for queuing source and destination transfers 

Intrachannel DMA transfers chaining via programmable linked-list into memory, 
supporting two execution modes: run-to-completion and link step mode 

Intrachannel and interchannel DMA transfers chaining via programmable DMA 
input triggers connection to DMA task completion events

Per linked-list item within a channel:

Separately programmed source and destination transfers

Programmable data handling between source and destination: byte-based 
reordering, packing or unpacking, padding or truncation, sign extension and 
left/right realignment 

Programmable number of data bytes to be transferred from the source, defining 
the block level

12 channels with linear source and destination addressing: either fixed or 
contiguously incremented addressing, programmed at a block level, between 
successive single transfers 

Four channels with 2D source and destination addressing: programmable signed 
address offsets between successive burst transfers (noncontiguous addressing 
within a block, combined with programmable signed address offsets between 
successive blocks, at a second 2D/repeated block level)

Support for scatter-gather (multibuffer transfers), data interleaving and 
deinterleaving via 2D addressing 

Programmable DMA request and trigger selection

Programmable DMA half-transfer and transfer complete events generation

Pointer to the next linked-list item and its data structure in memory, with automatic 
update of the DMA linked-list control registers

Debug:

Channel suspend and resume support

Channel status reporting including FIFO level and event flags

TrustZone support:

Support for secure and nonsecure DMA transfers, independently at a first channel 
level, and independently at a source/destination and link sublevels

Secure and nonsecure interrupts reporting, resulting from any of the respectively 
secure and nonsecure channels

TrustZone-aware AHB slave port, protecting any DMA secure resource (register, 
register field) from a nonsecure access

Privileged/unprivileged support:

Support for privileged and unprivileged DMA transfers, independently at 
channel level

Privileged-aware AHB slave port

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3.18 Low-power 

direct 

memory 

access controller (LPDMA)

The LPDMA controller is a bus master and system peripheral. The LPDMA is used to 
perform programmable data transfers between memory-mapped peripherals and/or 
memories via linked-lists, upon the control of an off-loaded CPU.

The LPDMA main features are:

Single bidirectional AHB master

Memory-mapped data transfers from a source to a destination:

Peripheral-to-memory

Memory-to-peripheral

Memory-to-memory

Peripheral-to-peripheral

Autonomous data transfers during Sleep and Stop modes

Transfers arbitration based on a 4-grade programmed priority at channel level:

One high-priority traffic class, for time-sensitive channels (queue 3)

Three low-priority traffic classes, with a weighted round-robin allocation for non 
time-sensitive channels (queues 0, 1, 2)

Per channel event generation, on any of the following events: transfer complete, or 
half-transfer complete, or data transfer error, or user setting error, and/or update 
linked-list item error, or completed suspension

Per channel interrupt generation, with separately programmed interrupt enable 
per event

Table 11. GPDMA1 channels implementation and usage 

Channel 

x

 Hardware parameters

Features

dma_fifo_

size[x]

dma_

addressing[x]

x = 0 to 11

2

0

Channel x (x = 0 to 11) is implemented with:
– a FIFO of 8 bytes, 2 words
– fixed/contiguously incremented addressing
These channels may be also used for GPDMA transfers, between an APB 
or AHB peripheral and SRAM.

x = 12  to 

15

4

1

Channel x (x = 12 to 15) is implemented with:
– a FIFO of 32 bytes, 8 words
– 2D addressing
These channels may be also used for GPDMA transfers, between 
a demanding AHB peripheral and SRAM, or for transfers from/to external 
memories.

Table 12. GPDMA1 autonomous mode and wake-up in low-power modes

Feature

Low-power modes

Autonomous mode and wake-up

GPDMA1 in Sleep, Stop 0 and Stop 1 modes

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Four concurrent DMA channels:

Intrachannel DMA transfers chaining via programmable linked-list into memory, 
supporting two execution modes: run-to-completion and link step mode 

Intrachannel and interchannel DMA transfers chaining via programmable DMA 
input triggers connection to DMA task completion events

Per linked-list item within a channel:

Separately programmed source and destination transfers

Programmable data handling between source and destination: byte-based 
padding or truncation, sign extension and left/right realignment 

Programmable number of data bytes to be transferred from the source, defining 
the block level

Linear source and destination addressing: either fixed or contiguously 
incremented addressing, programmed at a block level, between successive 
single transfers 

Programmable DMA request and trigger selection

Programmable DMA half-transfer and transfer complete events generation

Pointer to the next linked-list item and its data structure in memory, with automatic 
update of the DMA linked-list control registers

Debug:

Channel suspend and resume support

Channel status reporting and event flags

TrustZone support

Support for secure and nonsecure DMA transfers, independently at a first channel 
level, and independently at a source/destination and link sublevels

Secure and nonsecure interrupts reporting, resulting from any of the respectively 
secure and nonsecure channels

TrustZone-aware AHB slave port, protecting any DMA secure resource (register, 
register field) from a nonsecure access

Privileged/unprivileged support:

Support for privileged and unprivileged DMA transfers, independently at 
channel level

Privileged-aware AHB slave port

          

Table 13.  LPDMA1 channels implementation and usage 

Channel 

x

 Hardware parameters

Features

dma_fifo_

size[x]

dma_

addressing[x]

x = 0  to 3

0

0

Channel x (x = 0 to 3) is implemented with:
– no FIFO. Only a single source transfer cell is internally registered.
– fixed/contiguously incremented addressing

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3.19 Chrom-ART 

Accelerator controller (DMA2D)

The Chrom-ART Accelerator (DMA2D) is a specialized DMA dedicated to image 
manipulation. It can perform the following operations:

Filling a part or the whole of a destination image with a specific color

Copying a part or the whole of a source image into a part or the whole of a destination 
image

Copying a part or the whole of a source image into a part or the whole of a destination 
image with a pixel format conversion

Blending a part and/or two complete source images with different pixel format and copy 
the result into a part or the whole of a destination image with a different color format.

All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with 
indexed or direct color mode. The DMA2D has its own dedicated memories for CLUTs (color 
look-up tables).

The main DMA2D features are:

Single AHB master bus architecture

AHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT 
accesses that are 32-bit)

User programmable working area size

User programmable offset for sources and destination areas expressed in pixels or 
bytes expressed in pixels or bytes

User programmable sources and destination addresses on the whole memory space

Up to two sources with blending operation

Alpha value can be modified (source value, fixed value, or modulated value)

User programmable source and destination color format

Up to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct 
color coding

Two internal memories for CLUT storage in indirect color mode

Automatic CLUT loading or CLUT programming via the CPU

User programmable CLUT size

Internal timer to control AHB bandwidth

Six operating modes: register-to-memory, memory-to-memory, memory-to-memory 
with pixel format conversion, memory-to-memory with pixel format conversion and 
blending, memory-to memory with pixel format conversion, blending and fixed color 
foreground, and memory-to memory with pixel format conversion, blending and fixed 
color background

Area filling with a fixed color

Copy from an area to another

Copy with pixel format conversion between source and destination images

Copy from two sources with independent color format and blending

Table 14. LPDMA1 autonomous mode and wake-up in low-power modes

Feature

Low-power modes

Autonomous mode and wake-up

LPDMA1 in Sleep, Stop 0, Stop 1 and Stop 2 modes

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Output buffer byte swapping to support refresh of displays through parallel interface

Abort and suspend of DMA2D operations

Watermark interrupt on a user programmable destination line

Interrupt generation on bus error or access conflict

Interrupt generation on process completion

3.20 Interrupts 

and 

events

3.20.1 

Nested vectored interrupt controller (NVIC)

The devices embed an NVIC that is able to manage 16 priority levels and to handle up to 
125 maskable interrupt channels plus the 16 interrupt lines of the Cortex-M33.

The NVIC benefits are the following:

closely coupled NVIC giving low-latency interrupt processing

interrupt entry vector table address passed directly to the core

early processing of interrupts

processing of late arriving higher priority interrupts

support for tail chaining

processor state automatically saved

interrupt entry restored on interrupt exit with no instruction overhead

TrustZone support: NVIC registers banked across secure and nonsecure states

The NVIC hardware block provides flexible interrupt management features with minimal 
interrupt latency.

3.20.2 

Extended interrupt/event controller (EXTI)

The EXTI manages the individual CPU and system wake-up through configurable event 
inputs. It provides wake-up requests to the power control, and generates an interrupt 
request to the CPU NVIC and events to the CPU event input. For the CPU, an additional 
event generation block (EVG) is needed to generate the CPU event signal.

The EXTI wake-up requests allow the system to be woken up from Stop modes.

The interrupt request and event request generation can also be used in Run modes. 
The EXTI also includes the EXTI multiplexer I/O port selection.

The EXTI main features are the following:

All event inputs allowed to wake up the system

Configurable events (signals from I/Os or peripherals able to generate a pulse)

Selectable active trigger edge

Interrupt pending status register bit independent for the rising and falling edge

Individual interrupt and event generation mask, used for conditioning the CPU 
wake-up, interrupt, and event generation

Software trigger possibility

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TrustZone secure events

The access to control and configuration bits of secure input events can be made 
secure

EXTI I/O port selection

3.21 Cyclic 

redundancy 

check calculation unit (CRC)

The CRC is used to get a CRC code using a configurable generator with polynomial value 
and size.

Among other applications, the CRC-based techniques are used to verify data transmission 
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify 
the flash memory integrity. 

The CRC calculation unit helps to compute a signature of the software during runtime that 
can be ulteriorly compared with a reference signature generated at link-time and that can be 
stored at a given memory location.

3.22 CORDIC 

coprocessor 

(CORDIC)

The CORDIC coprocessor provides hardware acceleration of certain mathematical 
functions, notably trigonometric, commonly used in motor control, metering, signal 
processing and many other applications. It speeds up the calculation of these functions 
compared to a software implementation, allowing a lower operating frequency, or freeing up 
processor cycles in order to perform other tasks.

The CORDIC main features are:

24-bit CORDIC rotation engine

Circular and hyperbolic modes

Rotation and vectoring modes

Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root, 
natural logarithm

Programmable precision

Low-latency AHB slave interface

Results can be read as soon as ready without polling or interrupt

DMA read and write channels

Multiple register read/write by DMA

3.23 

Filter math accelerator (FMAC)

The FMAC performs arithmetic operations on vectors. It comprises a MAC 
(multiplier/accumulator) unit, together with address generation logic that allows it to index 
vector elements held in local memory.

The unit includes support for circular buffers on input and output that allows digital filters to 
be implemented. Both finite and infinite impulse response filters can be done.

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The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing 
up the processor for other tasks. In many cases it can accelerate such calculations 
compared to a software implementation, resulting in a speed-up of time critical tasks.

The FMAC main features are:

16 x 16-bit multiplier

24 + 2-bit accumulator with addition and subtraction

16-bit input and output data

256 x 16-bit local memory

Up to three areas can be defined in memory for data buffers (two inputs, one output), 
defined by programmable base address pointers and associated size registers

Input and output buffers can be circular

Filter functions: FIR, IIR (direct form 1)

Vector functions: dot product, convolution, correlation

AHB slave interface

DMA read and write data channels

3.24 

Flexible static memory controller (FSMC)

The FSMC includes two memory controllers:

NOR/PSRAM memory controller

NAND/memory controller

The FSMC is also named flexible memory controller (FMC).

The main features of the FSMC are the following:

Interface with static-memory mapped devices including:

Static random access memory (SRAM)

NOR flash memory/OneNAND flash memory

PSRAM (four memory banks)

NAND flash memory with ECC hardware to check up to 8 Kbytes of data

Ferroelectric RAM (FRAM)

8-,16-bit data bus width

Independent chip select control for each memory bank

Independent configuration for each memory bank

Write FIFO

3.24.1 LCD 

parallel 

interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It 
supports the Intel

®

 8080 and Motorola

®

 6800 modes, and is flexible enough to adapt to 

specific LCD interfaces. 

This LCD parallel interface capability makes it easy to build cost effective graphic 
applications using LCD modules with embedded controllers or high-performance solutions 
using external controllers with dedicated acceleration.

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3.24.2 

FSMC TrustZone security

When the TrustZone security is enabled, the whole FSMC banks are secure after reset. 
Nonsecure area can be configured using the TZSC MPCWMx controller:

FSMC NOR/PSRAM bank: 

Up to two nonsecure areas can be configured thought the TZSC MPCWM2 
controller with a 64-Kbyte granularity

FSMC NAND bank:

Can be either configured as fully secure or fully nonsecure using the TZSC 
MPCWM3 controller

The FSMC registers can be configured as secure through the TZSC controller.

3.25 Octo-SPI 

interface (OCTOSPI)

The devices embed two OCTOSPIs. The OCTOSPI supports most external serial memories 
such as serial PSRAMs, serial NAND and serial NOR flash memories, HyperRAMs™ and 
HyperFlash™ memories, with the following functional modes:

Indirect mode: all the operations are performed using the OCTOSPI registers.

Status-polling mode: the external memory status register is periodically read and 
an interrupt can be generated in case of flag setting.

Memory-mapped mode: the external memory is memory mapped and is seen by the 
system as if it were an internal memory supporting read and write operation.

The OCTOSPI supports the following protocols with associated frame formats:

the standard frame format with the command, address, alternate byte, dummy cycles, 
and data phase

the HyperBus

 frame format

The OCTOSPI offers the following features:

Three functional modes: Indirect, Status-polling, and Memory-mapped

Read and write support in Memory-mapped mode

Supports for single, dual, quad, and octal communication

Dual-quad mode, where eight bits can be sent/received simultaneously by accessing 
two quad memories in parallel.

SDR (single-data rate) and DTR (double-transfer rate) support

Data strobe support

Fully programmable opcode

Fully programmable frame format

HyperBus support

Integrated FIFO for reception and transmission

8-, 16-, and 32-bit data accesses allowed

DMA channel for Indirect mode operations

Interrupt generation on FIFO threshold, timeout, operation complete, and access error

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3.25.1 

OCTOSPI TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset. 

Up to two nonsecure areas can be configured thought the TZSC MPCWM1 and MPCWM5 
controllers with a granularity of 64 Kbytes.

The OCTOSPI registers can be configured as secure through the TZSC controller.

3.26 

OCTOSPI I/O manager (OCTOSPIM)

The OCTOSPI I/O manager is a low-level interface enabling:

efficient OCTOSPI pin assignment with a full I/O matrix (before alternate function map)

multiplex of Single-, Dual-, Quad-, Octal-SPI interfaces over the same bus and hence 
support memories embedded in a multichip package

The OCTOSPIM main features are:

Supports up to two single-, dual-, quad-, octal-SPI interfaces

Supports up to two ports for pin assignment

Fully programmable I/O matrix for pin assignment by function (data/control/clock)

3.27 

Delay block (DLYB)

The delay block (DLYB) is used to generate an output clock that is dephased from the input 
clock. The phase of the output clock must be programmed by the user application. The 
output clock is then used to clock the data received by another peripheral such as 
a SDMMC or Octo-SPI interface. The delay is voltage and temperature dependent, that may 
require the application to reconfigure and recenter the output clock phase with the received 
data.

The delay block main features are: 

Input clock frequency ranging from 25 to 160 MHz 

Up to 12 oversampling phases

3.28 

Analog-to-digital converter (ADC1 and ADC4)

The devices embed two successive approximation analog-to-digital converters.

          

Table 15. ADC features 

ADC modes/features

(1)

ADC1

ADC4

Resolution

14 bits

12 bits

Maximum sampling speed for maximum resolution

2.5 Msps

2.5 Msps

Hardware offset calibration

X

X

Hardware linearity calibration

X

-

Single-ended inputs

X

X

Differential inputs

X

-

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3.28.1 Analog-to-digital converter 1 (ADC1)

The ADC1 is a 14-bit ADC successive approximation analog-to-digital converter.

This ADC has up to 20 multiplexed channels. A/D conversion of the various channels can 
be performed in Single, Continuous, Scan or Discontinuous mode. The result of the ADC is 
stored in a left-aligned or right-aligned 32-bit data register.

This ADC is mapped on the AHB bus to allow fast data handling. The analog watchdog 
features allow the application to detect if the input voltage goes outside the user-defined 
high or low thresholds.

A built-in hardware over sampler allows analog performances to be improved while 
off-loading the related computational burden from the CPU.

An efficient low-power mode is implemented to allow very low consumption at low 
frequency.
The ADC1 main features are:

High-performance features

14-, 12-, 10-, or 8-bit configurable resolution

A/D conversion time independent from the AHB bus clock frequency

Faster conversion time by lowering resolution

Management of single-ended or differential inputs (programmable per channels)

Fast data handling thanks to the AHB slave bus interface 

Self-calibration (both offset and linearity)

Channel-wise programmable sampling time

Flexible sampling time control

Up to four injected channels (analog inputs assignment to regular or injected 
channels is fully configurable)

Fast context switching thanks to the hardware assistant that prepares the context 
of the injected channels 

Injected channel conversion

X

-

Oversampling 

up to x1024

up to x256

Data register

32 bits

16 bits

DMA support

X

X

Parallel data output to MDF

X

-

Autonomous mode

-

X

Offset compensation

X

-

Gain compensation

X

-

Number of analog watchdogs

3

3

Wake-up from Stop mode

-

X

(2)

1. X = supported.

2. Wake-up supported from Stop 0, Stop 1 and Stop 2 modes.

Table 15. ADC features (continued)

ADC modes/features

(1)

ADC1

ADC4

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Data alignment with in-built data coherency

Data can be managed by GPDMA for regular channel conversions with FIFO

Data can be routed to MDF for post processing

Four dedicated data registers for the injected channels

Oversampler

32-bit data register

Oversampling ratio adjustable from 2 to 1024

Programmable data right and left shift

Data preconditioning

Gain compensation

Offset compensation

Low-power features

Speed adaptive low-power mode to reduce ADC consumption when operating at 
low frequency

Slow bus frequency application while keeping optimum ADC performance

Automatic control to avoid ADC overrun in low AHB bus clock frequency 
application (autodelayed mode)

ADC features an external analog input channel:

Up to 17 channels from dedicated GPIO pads

Three additional internal dedicated channels:

One channel for internal reference voltage (V

REFINT

)

One channel for internal temperature sensor (V

SENSE

)

One channel for V

BAT 

monitoring channel (V

BAT

/4)

Start-of-conversion can be initiated:

by software for both regular and injected conversions

by hardware triggers with configurable polarity (internal timers events or GPIO 
input events) for both regular and injected conversions

Conversion modes

Single mode: the ADC converts a single channel. The conversion is triggered by 
a special event.

Scan mode: the ADC scans and converts a sequence of channels. 

Continuous mode: the ADC converts continuously selected inputs.

Discontinuous mode: the ADC converts a subset of the conversion sequence.

Interrupt generation when the ADC is ready, at end of sampling, end of conversion 
(regular or injected), end of sequence conversion (regular or injected), analog 
watchdog 1, 2 or 3 or when an overrun event occurs

Three analog watchdogs

Filtering to ignore out-of-range data

ADC input range: V

SSA

 <

 

V

IN 

< V

REF+

Note:

The ADC1 analog block clock frequency must be between 5 MHz and 55 MHz.

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3.28.2 Analog-to-digital converter 4 (ADC4)

The 12-bit ADC4 is a successive approximation analog-to-digital converter. It has up to 
25 multiplexed channels allowing it to measure signals from 19 external and six internal 
sources. A/D conversion of the various channels can be performed in Single, Continuous, 
Scan or Discontinuous mode. The result of the ADC is stored in a left-aligned or 
right-aligned 16-bit data register.

The analog watchdog feature allows the application to detect if the input voltage goes 
outside the user-defined higher or lower thresholds.

An efficient low-power mode is implemented to allow very low consumption at low 
frequency. The ADC4 is autonomous in low-power modes down to Stop 2 mode.

A built-in hardware oversampler allows analog performances to be improved while 
off-loading the related computational burden from the CPU.

The ADC4 main features are:

High performance

12-, 10-, 8- or, 6-bit configurable resolution

A/D conversion time: 0.4 µs for 12-bit resolution (2.5 MHz), faster conversion 
times obtained by lowering resolution

Self-calibration

Programmable sampling time

Data alignment with built-in data coherency

DMA support

Low-power

HCLK frequency reduced for low-power operation while still keeping optimum 
ADC performance

Wait mode: ADC overrun prevented in applications with low frequency HCLK 

Auto-off mode: ADC automatically powered off except during the active 
conversion phase, dramatically reducing the ADC power consumption

Autonomous mode: In low-power modes down to Stop 2 mode, the ADC4 is 
automatically switched on when a trigger occurs to start conversion, and it is 
automatically switched off after conversion. Data are transferred in SRAM 
with DMA.

ADC4 interrupts wake up the device from Stop 0, Stop 1, and Stop 2 modes.

Analog input channels

Up to 19 external analog inputs

One channel for the internal temperature sensor (V

SENSE

One channel for the internal reference voltage (V

REFINT

)

One channel for the internal digital core voltage (V

CORE

One channel for monitoring the external VBAT power supply pin

Connection to two DAC internal channels

Start-of-conversion can be initiated:

By software

By hardware triggers with configurable polarity (timer events or GPIO input 
events) 

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Conversion modes

Conversion of a single channel or scan of a sequence of channels

Selected inputs converted once per trigger in Single mode 

Selected inputs converted continuously in Continuous mode

Discontinuous mode

Interrupt generation at the end of sampling, end of conversion, end of sequence 
conversion, and in case of analog watchdog or overrun events, with wake-up from Stop 
capability

Analog watchdog

Oversampler

16-bit data register

Oversampling ratio adjustable from 2 to 256

Programmable data shift up to 8 bits

ADC supply requirements: 1.62 to 3.6 V

ADC input range: V

SSA

 < V

IN

 < V

REF+

Note:

The ADC4 analog block clock frequency must be between 140 kHz and 55 MHz.

3.28.3 Temperature 

sensor

The temperature sensor generates a voltage V

SENSE

 that varies linearly with temperature. 

The temperature sensor is internally connected to ADC1 and ADC4 input channel that is 
used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the 
temperature measurement. As the offset of the temperature sensor varies from chip to chip 
due to process variation, the uncalibrated internal temperature sensor is suitable for 
applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is 
individually factory-calibrated by ST. The temperature sensor factory calibration data are 
stored by STMicroelectronics in the system memory area, accessible in read-only mode.

          

Table 16. Temperature sensor calibration values 

Calibration 

value name

Description

Memory address

TS_CAL1

Temperature sensor 14-bit raw data acquired by ADC1

 

at 30 °C (± 5 °C), V

DDA

 = V

REF+

 = 3.0 V (± 10 mV)

0x0BFA 0710 - 0x0BFA 0711

TS_CAL2

Temperature sensor 14-bit raw data acquired by ADC1 

 

at 130 °C (± 5 °C), V

DDA

 = V

REF+

 = 3.0 V (± 10 mV)

0x0BFA 0742 - 0x0BFA 0743

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3.28.4 

Internal voltage reference (VREFINT)

The VREFINT provides a stable (bandgap) voltage output for the ADC and the comparators. 
The VREFINT is internally connected to ADC1 and ADC4 input channels. 

The precise voltage of VREFINT is individually measured for each part by 
STMicroelectronics during production test and stored in the system memory area. It is 
accessible in read-only mode.

          

3.28.5 V

BAT

 battery voltage monitoring

This embedded hardware enables the application to measure the V

BAT

 battery voltage using 

ADC1 or ADC4 input channel. As the V

BAT

 voltage may be higher than the V

DDA

, and thus 

outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 
four. As a consequence, the converted digital value is a quarter of the V

BAT

 voltage.

3.29 Digital-to-analog 

converter 

(DAC)

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be 
configured in 8- or 12-bit mode and may be used with the DMA controller. In 12-bit mode, 
the data may be left- or right-aligned. 

The DAC features two output channels, each with its own converter. In dual DAC channel 
mode, conversions can be done independently or simultaneously when both channels are 
grouped together for synchronous update operations. An input reference pin, VREF+ 
(shared with others analog peripherals) is available for better resolution. An internal 
reference can also be set on the same input.

The DAC_OUTx pin can be used as general-purpose input/output (GPIO) when the DAC 
output is disconnected from output pad and connected to on chip peripheral. The DAC 
output buffer can be optionally enabled to allow a high drive output current. An individual 
calibration can be applied on each DAC output channel. The DAC output channels support 
a low-power mode, the sample and hold mode.

The digital interface supports the following features:

One DAC interface, maximum two output channels

Left or right data alignment in 12-bit mode

Synchronized update capability

Noise-wave and triangular-wave generation

Sawtooth wave generation

Dual DAC channel for independent or simultaneous conversions

DMA capability for each channel including DMA underrun error detection

Double data DMA capability to reduce the bus activity

External triggers for conversion

DAC output channel buffered/unbuffered modes

Table 17. Internal voltage reference calibration values

Calibration value name

Description

Memory address

VREFINT_CAL

14-bit raw data acquired by ADC1 

 

at 30 °C (± 5 °C), V

DDA

 = V

REF+

 = 3.0 V (± 10 mV)

0x0BFA 07A5 - 0x0BFA 07A6

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Buffer offset calibration

Each DAC output can be disconnected from the DAC_OUTx output pin

DAC output connection to on chip peripherals

Sample and hold mode for low-power operation in Stop mode. The DAC voltage can 
be changed autonomously with the DMA while the device is in Stop mode.

Autonomous mode to reduce the power consumption for the system

Voltage reference input

3.30 Voltage 

reference buffer (VREFBUF)

The devices embed a voltage reference buffer that can be used as voltage reference for 
ADCs, DACs and also as voltage reference for external components through the 
VREF+ pin.

Figure 6. VREFBUF block diagram

The internal voltage reference buffer supports four voltages: 1.5 V, 1.8 V, 2.048 V, and 2.5 V.

An external voltage reference can be provided through the VREF+ pin when the internal 
voltage reference buffer is off.

The VREF+ pin is double-bonded with VDDA on some packages. In these packages, the 
internal voltage reference buffer is not available.

3.31 Comparators 

(COMP)

The devices embed two rail-to-rail comparators with programmable reference voltage 
(internal or external), hysteresis and speed (low speed for low power) and with selectable 
output polarity.

The reference voltage can be one of the following:

External I/O

DAC output channels

Internal reference voltage or submultiple (1/4, 1/2, 3/4)

MSv64430V2

+

-

V

REFINT

VREF+

VSSA

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All comparators can wake up from Stop 0, Stop 1 and Stop 2 modes, generate interrupts and 
breaks for the timers and can also be combined into a window comparator.

3.32 

Operational amplifiers (OPAMP)

The devices embed two operational amplifiers with external or internal follower routing and 
PGA capability.

The operational amplifier features:

Low-input bias current

Low-offset voltage

Low-power mode

Rail-to-rail input

3.33 

Multifunction digital filter (MDF) and audio digital filter (ADF)

The table below lists the set of features implemented into the MDF and the ADF. 

          

3.33.1 

Multifunction digital filter (MDF)

The MDF is a high-performance module dedicated to the connection of external sigma-delta 
(

Σ∆

) modulators. It is mainly targeted for the following applications:

audio capture signals

motor control

metering

The MDF features six digital serial interfaces (SITFx) and digital filters (DFLTx) with flexible 
digital processing options to offer up to 24-bit final resolution. 

The DFLTx of the MDF also include the filters of the ADF (audio digital filter).

Table 18. MDF features 

MDF modes/features

(1)

1. X = supported.

ADF1

MDF1

Number of filters (DFLTx) and serial interfaces (SITFx)

1

6

ADF_CKI0 / MDF_CKIy connected to pins

-

X

Sound activity detection (SAD)

X

-

RXFIFO depth (number of 24-bit words)

4

4

ADC connected to ADCITF1

-

ADC1

ADC connected to ADCITF2

-

-

Motor dedicated features (SCD, OLD, OEC, INT, snapshot, break)

-

Main path with CIC4, CIC5

X

X

Main path with CIC1,2, 3 or FastSinc

-

X

RSFLT, HPF, SAT, SCALE, DLY, Discard functions

X

X

Autonomous in Stop mode

X

(2)

2. Stop 0, Stop 1 and Stop 2 modes only.

X

(3)

3. Stop 0 and Stop 1 modes only.

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The MDF can receive, via its serial interfaces, streams coming from various digital sensors.

The MDF supports the following standards allowing the connection of various 

ΣΔ

 modulator 

sensors:

SPI interface

Manchester coded 1-wire interface

PDM interface

A flexible BSMX (bitstream matrix) allows the connection of any incoming bitstream to any 
filter.

The MDF converts an input data stream into clean decimated digital data words. This 
conversion is done thanks to low-pass digital filters and decimation blocks. In addition it is 
possible to insert a high-pass filter or DC offset correction block.

The conversion speed and resolution are adjustable according to configurable parameters 
for digital processing: filter type, filter order, decimation ratio, integrator length. The 
maximum output data resolution is up to 24 bits. There are two conversion modes: single 
conversion and continuous modes. The data can be automatically stored in a system RAM 
buffer through DMA, thus reducing the software overhead. 

A flexible trigger interface can be used to control the conversion start. This timing control 
can trigger simultaneous conversions or insert a programmable delay between conversions.

The MDF features an OLD (out-off limit detectors) function. There is one OLD for each 
digital filter chain. Independent programmable thresholds are available for each OLD, 
making it very suitable for overcurrent detection. 

An SCD (short circuit detector) is also available for every selected bitstream. The SCD is 
able to detect a short-circuit condition with a very short latency. Independent programmable 
thresholds are offered in order to define the short circuit condition.

All the digital processing is performed using only the kernel clock. The MDF requests the 
bus interface clock (AHB clock) only when data must be transferred or when a specific event 
requests the attention of the system processor.

The MDF main features are:

AHB interface

Six serial digital inputs:

configurable SPI interface to connect various digital sensors

configurable Manchester coded interface support

compatible with PDM interface to support digital microphones

Two common clock input/output for 

Σ∆

 modulators

Flexible BSMX for connection between filters and digital inputs

Two inputs to connect the internal ADCs

Six flexible digital filter paths, including:

A configurable CIC filter:
- Can be split into two CIC filters: high-resolution filter and out-off limit detector
- Can be configured in Sinc

4

 filter 

- Can be configured in Sinc

5

 filter 

- Adjustable decimation ratio

A reshape filter to improve the out-off band rejection and in-band ripple

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A high-pass filter to cancel the DC offset

An offset error cancellation

Gain control

Saturation blocks

An out-off limit detector

Short-circuit detector

Clock absence detector

16- or 24-bit signed output data resolution

Continuous or single conversion

Possibility to delay independently each bitstream

Various trigger possibilities

Break generation on out-of limit or short-circuit detector events

Autonomous functionality in Stop modes

DMA can be used to read the conversion data

Interrupts services

3.33.2 

Audio digital filter (ADF)

The ADF is a high-performance module dedicated to the connection of external 

Σ∆

 

modulators. It is mainly targeted for the following applications:

audio capture signals

metering

The ADF features one digital serial interface (SITF0) and one digital filter (DFLT0) with 
flexible digital processing options to offer up to 24-bit final resolution.

The DLFT0 of the ADF is a subset of the digital filters included into the MDF.

The ADF serial interface supports several standards allowing the connection of various 

Σ∆

 

modulator sensors:

SPI interface

Manchester coded 1-wire interface

PDM interface

A flexible BSMX allows the connection of any incoming bitstream to any filter.

The ADF converts an input data stream into clean decimated digital data words. This 
conversion is done thanks to low-pass digital filters and decimation blocks. In addition it is 
possible to insert a high-pass filter or a DC offset correction block.

The conversion speed and resolution are adjustable according to configurable parameters 
for digital processing: filter type, filter order, decimation ratio. The maximum output data 
resolution is up to 24 bits. There are two conversion modes: single conversion and 
continuous modes. The data can be automatically stored in a system RAM buffer through 
DMA, thus reducing the software overhead. 

A SAD (sound activity detector) is available for the detection of “speech-like” signals. The 
SAD is connected at the output of DFLT0. Several parameters can be programmed to adjust 
properly the SAD to the sound environment. The SAD can strongly reduce the power 
consumption by preventing the storage of samples into the system memory as long as the 
observed signal does not match the programmed criteria.

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A flexible trigger interface can be used to control the start of conversion of the ADF.

All the digital processing is performed using only the kernel clock. The ADF requests the bus 
interface clock (AHB clock) only when data must be transferred or when a specific event 
requests the attention of the system processor.

The ADF main features are:

AHB interface

One serial digital input:

Configurable SPI interface to connect various digital sensors

Configurable Manchester coded interface support

Compatible with PDM interface to support digital microphones

Two common clocks input/output for 

Σ∆

 modulators

Flexible BSMX for connection between filters and digital inputs

One flexible digital filter path, including:

A configurable CIC filter:
- Can be configured in Sinc

4

 filter 

- Can be configured in Sinc

5

 filter 

- Adjustable decimation ratio

A reshape filter to improve the out-off band rejection and in-band ripple

A high-pass filter to cancel the DC offset

Gain control

Saturation blocks

Clock absence detector

Sound activity detector

16- or 24-bit signed output data resolution

Continuous or single conversion

Possibility to delay independently each bitstream

Various trigger possibilities

Autonomous mode in Stop 0, Stop 1 and Stop 2 modes

Wake-up from Stop with all interrupts

DMA can be used to read the conversion data

Interrupts services

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3.34 Digital 

camera interface (DCMI)

The DCMI is a synchronous parallel interface able to receive a high-speed data flow from 
an external 8-, 10-, 12-, or 14-bit CMOS camera module. It supports different data formats: 
YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).

This interface is for use with black and white cameras, X24 and X5 cameras, and it is 
assumed that all preprocessing such as resizing is performed in the camera module.

The DCMI features are:

8-, 10-, 12-, or 14-bit parallel interface

Embedded/external line and frame synchronization

Continuous or snapshot mode

Crop feature

Supports the following data formats:

8/10/12/14-bit progressive video: either monochrome or raw Bayer

YCbCr 4:2:2 progressive video

RGB 565 progressive video

Compressed data: JPEG

3.35 Parallel 

synchronous slave interface (PSSI)

The PSSI and the DCMI use the same circuitry. As a result, these two peripherals cannot be 
used at the same time: when using the PSSI, the DCMI registers cannot be accessed, and 
vice versa. In addition, the PSSI and the DCMI share the same alternate functions and the 
same interrupt vector.

The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It 
enables the transmitter to send a data valid signal that indicates when the data is valid, and 
the receiver to output a flow control signal that indicates when it is ready to sample the data.

The PSSI peripheral main features are the following:

Slave mode operation

8-bit or 16-bit parallel data input or output

4-word (16-byte) FIFO

Data enable (PSSI_DE) alternate function input and ready (PSSI_RDY) alternate 
function output

When selected, these inputs can either enable the transmitter to indicate when the data is 
valid, or allow the receiver to indicate when it is ready to sample the data, or both.

3.36 

Touch sensing controller (TSC)

The TSC provides a simple solution to add capacitive sensing functionality to any 
application. A capacitive sensing technology is able to detect finger presence near 
an electrode that is protected from direct touch by a dielectric (such as glass or plastic). The 
capacitive variation introduced by the finger (or any conductive object) is measured using 
a proven implementation based on a surface charge transfer acquisition principle.

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The TSC is fully supported by the STMTouch touch sensing firmware library that is free to 
use and allows touch sensing functionality to be implemented reliably in the end application.

The TSC main features are the following:

Proven and robust surface charge transfer acquisition principle

Supports up to 22 capacitive sensing channels

Up to eight capacitive sensing channels can be acquired in parallel offering a very good 
response time

Spread spectrum feature to improve system robustness in noisy environments

Full hardware management of the charge transfer acquisition sequence

Programmable charge transfer frequency

Programmable sampling capacitor I/O pin

Programmable channel I/O pin

Programmable max count value to avoid long acquisition when a channel is faulty

Dedicated end of acquisition and max count error flags with interrupt capability

One sampling capacitor for up to three capacitive sensing channels to reduce the 
system components

Compatible with proximity, touchkey, linear and rotary touch sensor implementation

Designed to operate with STMTouch touch sensing firmware library

Note:

The number of capacitive sensing channels is dependent on the size of the packages and 
subject to I/O availability.

3.37 

True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the 
application as 32-bit samples. It is composed of a live entropy source (analog) and 
an internal conditioning component.

The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct 
a nondeterministic random bit generator (NDRBG).

The true random generator:

delivers 32-bit true random numbers, produced by an analog entropy source 
conditioned by a NIST SP800-90B approved conditioning stage

can be used as entropy source to construct a nondeterministic random bit generator 
(NDRBG)

produces four 32-bit random samples every 412 AHB clock cycles if f

AHB

 < 77 MHz 

(256 RNG clock cycles otherwise)

embeds startup and NIST SP800-90B approved continuous health tests (repetition 
count and adaptive proportion tests), associated with specific error management

can be disabled to reduce power consumption, or enabled with an automatic low-power 
mode (default configuration)

has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses 
only (else an AHB bus error is generated, and the write accesses are ignored)

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3.38 HASH 

hardware 

accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm 

 

(SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and 
the HMAC (keyed-hash message authentication code) algorithm. HMAC is suitable for 
applications requiring message authentication.

The HASH computes FIPS (Federal information processing standards) approved digests of 
length of 160, 224, 256 bits, for messages of up to (2

64

 – 1) bits. It also computes 128 bits 

digests for the MD5 algorithm.

The HASH main features are:

Suitable for data authentication applications, compliant with:

Federal Information Processing Standards Publication FIPS PUB 180-4, 

Secure 

Hash Standard 

(SHA-1 and SHA-2 family)

Federal Information Processing Standards Publication FIPS PUB 186-4, 

Digital 

Signature Standard (DSS)

Internet Engineering Task Force (IETF) Request For Comments RFC 1321, 

MD5 

Message-Digest Algorithm

Internet Engineering Task Force (IETF) Request For Comments RFC 2104, 

HMAC: Keyed-Hashing for Message Authentication 

and Federal Information 

Processing Standards Publication FIPS PUB 198-1, 

The Keyed-Hash Message 

Authentication Code (HMAC)

Fast computation of SHA-1, SHA-224, SHA-256, and MD5

82 (respectively 66) clock cycles for processing one 512-bit block of data using 
SHA-1 (respectively SHA-256) algorithm

66 clock cycles for processing one 512-bit block of data using MD5 algorithm

Corresponding 32-bit words of the digest from consecutive message blocks are added 
to each other to form the digest of the whole message:

Automatic 32-bit words swapping to comply with the internal little-endian 
representation of the input bit string

Word swapping supported: bits, bytes, half-words, and 32-bit words

Automatic padding to complete the input bit string to fit digest minimum block size of 
512 bits (16 × 32 bits)

Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words, 
corresponding to one block size

AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB 
error is generated)

8 × 32-bit words (H0 to H7) for output message digest

Automatic data flow control with support of direct memory access (DMA) using one 
channel. Single or fixed burst of 4 supported.

Interruptible message digest computation, on a per-32-bit word basis

Reloadable digest registers

Hashing computation suspend/resume mechanism, including using DMA

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3.39 

Timers and watchdogs

The devices include two advanced control timers, up to seven general-purpose timers, two 
basic timers, four low-power timers, two watchdog timers and two SysTick timers. 

The table below compares the features of the advanced control, general-purpose and basic 
timers.

          

3.39.1 Advanced-control 

timers (TIM1, TIM8)

The advanced-control timers can each be seen as a three-phase PWM multiplexed on six 
channels. They have complementary PWM outputs with programmable inserted 
dead-times. They can also be seen as complete general-purpose timers. 

The four independent channels can be used for:

Input capture

Output compare

PWM generation (edge or center-aligned modes) with full modulation capability 

 

(0 - 100%)

One-pulse mode output

In Debug mode, the advanced-control timer counter can be frozen and the PWM outputs 
disabled in order to turn off any power switches driven by these outputs.

Many features are shared with the general-purpose TIMx timers (described in the next 
section) using the same architecture, so the advanced-control timers can work together with 
the TIMx timers via the 

Timer Link

 feature for synchronization or event chaining.

Table 19. Timer feature comparison 

Timer type

Timer

Counter 

resolution

Counter 

type

Prescaler 

factor

DMA 

request 

generation

Capture/

compare 

channels

Complementary 

outputs

Advanced 

control

TIM1, TIM8

16 bits

Up, down, 

Up/down

Any integer 

between 1 and 

65536

Yes

4

3

General-

purpose

TIM2, TIM3, 

TIM4, TIM5

32 bits

Up, down, 

Up/down

Any integer 

between 1 and 

65536

Yes

4

No

General-

purpose

TIM15

16 bits

Up

Any integer 

between 1 and 

65536

Yes

2

1

General-

purpose

TIM16, 

TIM17

16 bits

Up

Any integer 

between 1 and 

65536

Yes

1

1

Basic

TIM6, TIM7

16 bits

Up

Any integer 

between 1 and 

65536

Yes

0

No

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3.39.2 General-purpose 

timers 

(TIM2, TIM3, TIM4, TIM5, TIM15,

 

TIM16, TIM17)

There are up to seven synchronizable general-purpose timers embedded in the 
STM32U575xx devices (see 

Table 19

 for differences). Each general-purpose timer can be 

used to generate PWM outputs, or act as a simple time base.

TIM2, TIM3, TIM4, and TIM5
They are full-featured general-purpose timers with 32-bit autoreload up/downcounter 
and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare, 
PWM, or one-pulse mode output. They can work together, or with the other 
general-purpose timers via the 

Timer Link

 feature for synchronization or event 

chaining.
The counters can be frozen in Debug mode.
All have independent DMA request generation and support quadrature encoders.

TIM15, 16 and 17
They are general-purpose timers with mid-range features.
They have 16-bit autoreload upcounters and 16-bit prescalers.

TIM15 has two channels and one complementary channel

TIM16 and TIM17 have one channel and one complementary channel

All channels can be used for input capture/output compare, PWM, or one-pulse 
mode output.
The timers can work together via the 

Timer Link

 feature for synchronization or event 

chaining. The timers have independent DMA request generation.
The counters can be frozen in Debug mode.

3.39.3 

Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as 
generic 16-bit timebase.

3.39.4 Low-power 

timers 

(LPTIM1, LPTIM2, LPTIM3, LPTIM4)

The devices embed four low-power timers. These timers have an independent clock and are 
running in Stop mode if they are clocked by HSI16, MSI, LSE, LSI, or an external clock. 
They are able to wake up the system from Stop mode.

LPTIM1, LPTIM3, and LPTIM4 are active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 is active in Stop 0 and Stop 1 mode.

The low-power timer supports the following features:

16-bit up counter with 16-bit autoreload register

3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128)

Selectable clock

Internal clock sources: LSE, LSI, HSI16, MSIK (LPTIM1, LPTIM3, LPTIM4 only) or 
APB clock (LPTIM2 only) 

External clock source over LPTIM input (working with no LP oscillator running, 
used by 

Pulse Counter

 application)

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16-bit ARR autoreload register

16-bit capture/compare register

Continuous/One-shot mode

Selectable software/hardware input trigger

Programmable digital glitch filter

Configurable output: pulse, PWM

Configurable I/O polarity

Encoder mode

Repetition counter

Up to 2 independent channels for:

Input capture

PWM generation (edge-aligned mode)

One-pulse mode output

Interrupt generation on 10 events

DMA request generation on the following events:

Update event

Input capture

3.39.5 Infrared 

interface 

(IRTIM)

An infrared interface (IRTIM) for remote control is available on the device. It can be used 
with an infrared LED to perform remote control functions. It uses internal connections with 
TIM16 and TIM17.

3.39.6 Independent 

watchdog 

(IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is 
clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently 
from the main clock, it can operate in Stop and Standby modes. It can be used either as 
a watchdog to reset the device when a problem occurs, or as a free running timer for 
application timeout management. It is hardware or software configurable through the option 
bytes. The counter can be frozen in Debug mode.

3.39.7 Window 

watchdog 

(WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It 
can be used as a watchdog to reset the device when a problem occurs. It is clocked from 
the main clock. It has an early warning interrupt capability and the counter can be frozen 
in Debug mode.

3.39.8 SysTick 

timer

The Cortex-M33 with TrustZone embeds two SysTick timers.

When TrustZone is activated, two SysTick timers are available:

SysTick, secure instance

SysTick, nonsecure instance

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When TrustZone is disabled, only one SysTick timer is available. This timer (secure or 
nonsecure) is dedicated to real-time operating systems, but can also be used as a standard 
down counter. It features:

A 24-bit down counter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0

Programmable clock source

3.40 

Real-time clock (RTC), tamper and backup registers

3.40.1 Real-time 

clock 

(RTC) 

The RTC supports the following features:

Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date, 
month, year, in BCD (binary-coded decimal) format

Binary mode with 32-bit free-running counter

Automatic correction for 28, 29 (leap year), 30, and 31 days of the month

Two programmable alarms

On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to 
synchronize it with a master clock

Reference clock detection: a more precise second source clock (50 or 60 Hz) can be 
used to enhance the calendar precision

Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal 
inaccuracy

Timestamp feature that can be used to save the calendar content. This function can be 
triggered by an event on the timestamp pin, or by a tamper event, or by a switch to 
V

BAT

 mode

17-bit autoreload wake-up timer (WUT) for periodic events with programmable 
resolution and period

TrustZone support:

RTC fully securable

Alarm A, alarm B, wake-up timer and timestamp individual secure or nonsecure 
configuration

Alarm A, alarm B, wake-up timer and timestamp individual privileged protection

The RTC is supplied through a switch that takes power either from the V

DD

 supply when 

present or from the VBAT pin.

The RTC clock sources can be one of the following:

32.768 kHz external crystal (LSE)

external resonator or oscillator (LSE)

internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)

high-speed external clock (HSE), divided by a prescaler in the RCC.

The RTC is functional in V

BAT

 mode and in all low-power modes when it is clocked by the 

LSE. When clocked by the LSI, the RTC is not functional in V

BAT

 mode, but is functional in 

all low-power modes except Shutdown mode.

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All RTC events (alarm, wake-up timer, timestamp) can generate an interrupt and wake-up 
the device from the low-power modes.

3.40.2 

Tamper and backup registers (TAMP)

The antitamper detection circuit is used to protect sensitive data from external attacks. 32 
32-bit backup registers are retained in all low-power modes and also in V

BAT

 mode. The 

backup registers, as well as other secrets in the device, are protected by this antitamper 
detection circuit with eight tamper pins and eleven internal tampers. The external tamper 
pins can be configured for edge detection, or level detection with or without filtering, or 
active tamper that increases the security level by auto checking that the tamper pins are not 
externally opened or shorted.

TAMP main features:

A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches, 
and HASH peripherals.

32 32-bit backup registers: 

The backup registers (TAMP_BKPxR) are implemented in the backup domain that 
remains powered-on by V

BAT

 when the V

DD

 power is switched off.

Up to 8 tamper pins for 8 external tamper detection events:

Active tamper mode: continuous comparison between tamper output and input to 
protect from physical open-short attacks 

Flexible active tamper I/O management: from 4 meshes (each input associated to 
its own exclusive output) to 7 meshes (single output shared for up to 7 tamper 
inputs)

Passive tampers: ultra-low-power edge or level detection with internal pull-up 
hardware management

Configurable digital filter

11 internal tamper events to protect against transient or environmental perturbation 
attacks:

Backup domain voltage monitoring 

Temperature monitoring

LSE monitoring 

RTC calendar overflow 

JTAG/SWD access if RDP different from 0 

Monotonic counter overflow 

RNG fault

Independent watchdog reset when tamper flag is already set

3 ADC4 watchdogs

Each tamper can be configured in two modes:

Hardware mode: immediate erase of secrets on tamper detection, including 
backup registers erase

Software mode: erase of secrets following a tamper detection launched by 
software

Any tamper detection can generate an RTC time stamp event.

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TrustZone support: 

Tamper secure or nonsecure configuration

Backup registers configuration in 3 configurable-size areas:
- 1 read/write secure area
- 1 write secure/read nonsecure area
- 1 read/write nonsecure area

Tamper configuration and backup registers privilege protection

Monotonic counter

3.41 Inter-integrated 

circuit interface (I2C)

The device embeds four I2C. Refer to 

Table 20

 for the features implementation.

The I

2

C bus interface handles communications between the microcontroller and the serial 

I

2

C bus. It controls all I

2

C bus-specific sequencing, protocol, arbitration, and timing. 

The I2C peripheral supports:

I

2

C-bus specification and user manual rev. 5 compatibility: 

Slave and Master modes, multimaster capability 

Standard-mode (Sm), with a bit rate up to 100 Kbit/s

Fast-mode (Fm), with a bit rate up to 400 Kbit/s 

Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os

7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

Programmable setup and hold times 

Optional clock stretching 

System management bus (SMBus) specification rev 3.0 compatibility: 

Hardware PEC (packet error checking) generation and verification with 
ACK control 

Address resolution protocol (ARP) support 

SMBus alert 

Power system management protocol (PMBus) specification rev 1.3 compatibility 

Independent clock: a choice of independent clock sources allowing the I

2

communication speed to be independent from the PCLK reprogramming 

Autonomous functionality in Stop modes with wake-up from Stop capability

Programmable analog and digital noise filters

1-byte buffer with DMA capability

          

Table 20. I2C implementation 

I2C features

(1)

I2C1

I2C2

I2C3

I2C4

Standard-mode (up to 100 Kbit/s)

X

X

X

X

Fast-mode (up to 400 Kbit/s)

X

X

X

X

Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

X

X

X

X

Programmable analog and digital noise filters

X

X

X

X

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3.42 Universal 

synchronous/asynchronous receiver transmitter 

(USART/UART)

 

and low-power universal asynchronous receiver transmitter 
(LPUART)

The devices embed three universal synchronous receiver transmitters (USART1, USART2, 
and USART3), two universal asynchronous receiver transmitters (UART4, UART5) and one 
low-power universal asynchronous receiver transmitter (LPUART1).

          

SMBus/PMBus hardware support

X

X

X

X

Independent clock

X

X

X

X

Autonomous in Stop 0, Stop 1 mode with wake-up capability

X

X

X

X

Autonomous in Stop 2 mode with wake-up capability 

-

-

X

-

1. X: supported

Table 20. I2C implementation (continued)

I2C features

(1)

I2C1

I2C2

I2C3

I2C4

Table 21. USART, UART, and LPUART features 

USART modes/features

(1)

1. X = supported.

USART1/2/3

UART4/5

LPUART1

Hardware flow control for modem

X

X

X

Continuous communication using DMA

X

X

X

Multiprocessor communication

X

X

X

Synchronous SPI mode (master/slave)

X

-

-

Smartcard mode

X

-

-

Single-wire half-duplex communication

X

X

X

IrDA SIR ENDEC block

X

X

-

LIN mode

X

X

-

Dual-clock domain and wake-up from Stop mode

X

(2)

2.

Wake-up supported from Stop 0 and Stop 1 modes. 

X

(2)

X

(3)

3.

Wake-up supported from Stop 0, Stop 1 and Stop 2 modes. 

Receiver timeout interrupt

X

X

-

Modbus communication

X

X

-

Auto-baud rate detection

-

Driver enable

X

X

X

USART data length

7, 8 and 9 bits

Tx/Rx FIFO

X

X

X

Tx/Rx FIFO size 

8 bytes

Autonomous mode

X

X

X

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3.42.1 Universal 

synchronous/asynchronous receiver transmitter

 

(USART/UART)

The USART offers a flexible means to perform full-duplex data exchange with external 
equipment requiring an industry standard NRZ asynchronous serial data format. A very wide 
range of baud rates can be achieved through a fractional baud rate generator. 

The USART supports both synchronous one-way and half-duplex single-wire 
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA 
(infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS). 
Multiprocessor communications are also supported.

High-speed data communications up to 20 Mbauds are possible by using the DMA (direct 
memory access) for multibuffer configuration.

The USART main features are:

Full-duplex asynchronous communication 

NRZ standard format (mark/space)

Configurable oversampling method by 16 or 8 to achieve the best compromise 
between speed and clock tolerance

Baud rate generator systems

Two internal FIFOs for transmit and receive data

 

Each FIFO can be enabled/disabled by software and come with a status flag.

A common programmable transmit and receive baud rate 

Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK

Auto baud rate detection

Programmable data word length (7, 8 or 9 bits)

Programmable data order with MSB-first or LSB-first shifting

Configurable stop bits (1 or 2 stop bits)

Synchronous SPI Master/Slave mode and clock output/input for synchronous 
communications

SPI slave transmission underrun error flag

Single-wire half-duplex communications

Continuous communications using DMA

Received/transmitted bytes are buffered in reserved SRAM using centralized DMA

Separate enable bits for transmitter and receiver

Separate signal polarity control for transmission and reception

Swappable Tx/Rx pin configuration

Hardware flow control for modem and RS-485 transceiver

Communication control/error detection flags

Parity control:

Transmits parity bit

Checks parity of received data byte

Interrupt sources with flags

Multiprocessor communications: wake-up from Mute mode by idle line detection or 
address mark detection

Autonomous functionality in Stop mode with wake-up from stop capability

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LIN master synchronous break send capability and LIN slave break detection capability

13-bit break generation and 10/11-bit break detection when USART is hardware 
configured for LIN

IrDA SIR encoder decoder supporting 3/16-bit duration for Normal mode

Smartcard mode

Supports the T = 0 and T = 1 asynchronous protocols for smartcards as defined in 
the ISO/IEC 7816-3 standard

0.5 and 1.5 stop bits for Smartcard operation

Support for Modbus communication

Timeout feature

CR/LF character recognition

3.42.2 Low-power 

universal 

asynchronous receiver transmitter (LPUART)

The LPUART supports bidirectional asynchronous serial communication with minimum 
power consumption. It also supports half-duplex single-wire communication and modem 
operations (CTS/RTS). It allows multiprocessor communication.

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame 
while having an extremely low energy consumption. Higher-speed clock can be used to 
reach higher baud rates.

The LPUART interface can be served by the DMA controller.

The LPUART main features are:

Full-duplex asynchronous communications

NRZ standard format (mark/space)

Programmable baud rate

From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source

Higher baud rates can be achieved by using a higher frequency clock source

Two internal FIFOs to transmit and receive data

 

Each FIFO can be enabled/disabled by software and come with status flags for 
FIFO states.

Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK 

Programmable data word length (7 or 8 or 9 bits)

Programmable data order with MSB-first or LSB-first shifting

Configurable stop bits (1 or 2 stop bits)

Single-wire half-duplex communications

Continuous communications using DMA

Received/transmitted bytes are buffered in reserved SRAM using centralized DMA

Separate enable bits for transmitter and receiver

Separate signal polarity control for transmission and reception

Swappable Tx/Rx pin configuration

Hardware flow control for modem and RS-485 transceiver 

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Transfer detection flags:

Receive buffer full

Transmit buffer empty

Busy and end of transmission flags

Parity control:

Transmits parity bit

Checks parity of received data byte

Four error detection flags:

Overrun error

Noise detection

Frame error

Parity error

Interrupt sources with flags

Multiprocessor communications: wake-up from Mute mode by idle line detection or 
address mark detection

Autonomous functionality in Stop mode with wake-up from Stop capability

3.43 

Serial peripheral interface (SPI)

The devices embed three serial peripheral interfaces (SPI) that can be used to 
communicate with external devices while using the specific synchronous protocol. The SPI 
protocol supports half-duplex, full-duplex, and simplex synchronous, serial communication 
with external devices. 

The interface can be configured as master or slave and can operate in multislave or 
multimaster configurations. The device configured as master provides communication clock 
(SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be applied 
optionally just to setup communication with concrete slave and to assure it handles the data 
flow properly. The Motorola

®

 data format is used by default, but some other specific modes 

are supported as well.

The SPI main features are:

Full-duplex synchronous transfers on three lines

Half-duplex synchronous transfer on two lines (with bidirectional data line)

Simplex synchronous transfers on two lines (with unidirectional data line)

4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only

Multimaster or multislave mode capability

Dual-clock domain, separated clock for the peripheral kernel that can be independent 
of PCLK

Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode

Protection of configuration and setting

Hardware or software management of SS for both master and slave

Adjustable minimum delays between data and between SS and data flow

Configurable SS signal polarity and timing, MISO x MOSI swap capability

Programmable clock polarity and phase

Programmable data order with MSB-first or LSB-first shifting

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Programmable number of data within a transaction to control SS and CRC

Dedicated transmission and reception flags with interrupt capability

SPI Motorola

®

 and Texas Instruments

®

 formats support

Hardware CRC feature can secure communication at the end of transaction by:

Adding CRC value in Tx mode

Automatic CRC error checking for Rx mode

Error detection with interrupt capability in case of data overrun, CRC error, data 
underrun at slave, mode fault at master

Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability

Programmable number of data in transaction

Configurable FIFO thresholds (data packing)

Configurable behavior at slave underrun condition (support of cascaded circular 
buffers)

Autonomous functionality in Stop modes (handling of the transaction flow and required 
clock distribution) with wake-up from stop capability

Optional status pin RDY signalizing the slave device ready to handle the data flow.

          

3.44 Serial 

audio 

interfaces (SAI)

The devices embed two SAIs. Refer to 

Table 23: SAI implementation

 for the features 

implementation. The SAI bus interface handles communications between the 
microcontroller and the serial audio protocol. 

The SAI peripheral supports:

Two independent audio subblocks that can be transmitters or receivers with their 
respective FIFO

8-word integrated FIFOs for each audio subblock

Synchronous or asynchronous mode between the audio subblocks

Master or slave configuration independent for both audio subblocks

Clock generator for each audio block to target independent audio frequency sampling 
when both audio subblocks are configured in master mode

Table 22. SPI features 

SPI feature

SPI1, SPI2

(full feature set instances)

SPI3 

(limited feature set instance)

Data size

Configurable from 4 to 32-bit

8/16-bit

CRC computation

CRC polynomial length 

configurable from 5 to 33-bit

CRC polynomial length 

configurable from 9 to 17-bit

Size of FIFOs

16x 8-bit

8x 8-bit

Number of transfered data

Unlimited, expandable

Up to 1024, no data counter

Autonomous in Stop 0, Stop 1 mode 
with wake-up capability

Yes

Yes

Autonomous in Stop 2 mode with 
wake-up capability

No

Yes

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Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit

Peripheral with large configurability and flexibility allowing to target as example the 
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and 
SPDIF out

Up to 16 slots available with configurable size and with the possibility to select which 
ones are active in the audio frame

Number of bits by frame may be configurable

Frame synchronization active level configurable (offset, bit length, level)

First active bit position in the slot is configurable

LSB first or MSB first for data transfer

Mute mode

Stereo/mono audio frame capability

Communication clock strobing edge configurable (SCK)

Error flags with associated interrupts if enabled respectively

Overrun and underrun detection

Anticipated frame synchronization signal detection in Slave mode

Late frame synchronization signal detection in Slave mode

Codec not ready for the AC’97 mode in reception

Interruption sources when enabled:

Errors

FIFO requests

DMA interface with two dedicated channels to handle access to the dedicated 
integrated FIFO of each SAI audio subblock.

          

3.45 Secure 

digital 

input/output and MultiMediaCards interface 

(SDMMC)

The SDMMC (SD/SDIO embedded MultiMediaCard 

e

•MMC™ host interface) provides 

an interface between the AHB bus and SD memory cards, SDIO cards and 

e

•MMC devices.

Table 23. SAI implementation 

SAI features

(1)

1. X: supported

SAI1

SAI2

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97

X

X

Mute mode

X

X

Stereo/mono audio frame capability.

X

X

16 slots 

X

X

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit

X

X

FIFO size 

X (8 words)

X (8 words)

SPDIF

X

X

PDM

X

-

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The MultiMediaCard system specifications are available through the MultiMediaCard 
association website at www.mmca.org, published by the MMCA technical committee.

SD memory card and SD I/O card system specifications are available through the SD card 
Association website at www.sdcard.org.

The SDMMC features include the following:

Compliance with Embedded MultiMediaCard System Specification Version 5.1 
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit 
(HS200 SDMMC_CK speed limited to maximum allowed I/O speed) (HS400 is not 
supported).

Full compatibility with previous versions of MultiMediaCards (backward compatibility).

Full compliance with 

SD memory card specifications version 6.0

(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and 
UHS-II mode not supported).

Full compliance with 

SDIO card specification version 4.0

Card support for two different databus modes: 1-bit (default) and 4-bit
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and 
UHS-II mode not supported).

Data transfer up to 208 Mbyte/s for the 8-bit mode
(Depending maximum allowed I/O speed).

Data and command output enable signals to control external bidirectional drivers

IDMA linked list support

The MultiMediaCard/SD bus connects cards to the host.

The current version of the SDMMC supports only one SD/SDIO/

e

•MMC card at any one 

time and a stack of 

e

•MMC.

          

When SDMMC peripherals are used simultaneously:

Only one can be used in 

e

•MMC with 8-bit bus width.

The SDMMC1 SDIO voltage switch use is mutually exclusive with SDMMC2 interfacing 

e

•MMC with 8-bit bus width, as follows:

If SDMMC1 has to support SDIO UHS-I modes (SDR12, SDR25, SDR50, 
SDR104, or DDR50), SDMMC2 cannot support 

e

•MMC with 8-bit bus width.

if SDMMC2 has to support 

e

•MMC with 8-bit bus width, SDMMC1 supports only 

SDIO default mode and high-speed mode.

Table 24. SDMMC features 

SDMMC modes/features

(1)

1. X = supported.

SDMMC1

SDMMC2

Variable delay (SDR104, HS200)

X

X

SDMMC_CKIN

X

-

SDMMC_CDIR, SDMMC_D0DIR

X

-

SDMMC_D123DIR

X

-

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3.46 

Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of one CAN module, a shared 
message RAM memory and a configuration block. 

The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification 
version 2.0 part A, B) and CAN FD protocol specification version 1.0.

A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and 
transmits FIFOs.

The FDCAN main features are:

Conform with CAN protocol version 2.0 part A, B, and ISO 11898-1: 2015, -4

CAN FD with maximum 64 data bytes supported

CAN error logging

AUTOSAR and J1939 support

Improved acceptance filtering

2 receive FIFOs of three payloads each (up to 64 bytes per payload)

Separate signaling on reception of high priority messages

Configurable transmit FIFO / queue of three payloads (up to 64 bytes per payload)

Configurable transmit Event FIFO 

Programmable loop-back test mode

Maskable module interrupts

Two clock domains: APB bus interface and CAN core kernel clock

Power-down support

3.47 

USB on-the-go full-speed (OTG_FS)

The devices embed a USB OTG full-speed device/host/OTG peripheral with integrated 
transceivers. The USB OTG_FS peripheral is compliant with the USB 2.0 specification and 
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports 
suspend/resume. 

This interface requires a precise 48 MHz clock that can be generated from the internal main 
PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator 
(HSI48) in automatic-trimming mode. The synchronization for this oscillator can be taken 
from the USB data stream itself (SOF signalization) that allows crystal less operation.

The OTG_FS features are: 

USB-IF certified to the Universal Serial Bus Specification Rev 2.0

On-chip full-speed PHY

Full support (PHY) for the optional OTG (on-the-go) protocol detailed in the OTG 
Supplement Rev 2.0 specification

Integrated support for A-B device identification (ID line)

Integrated support for host negotiation protocol (HNP) and session request 
protocol (SRP)

Allows host to turn V

BUS

 off to conserve battery power in OTG applications

Supports OTG monitoring of V

BUS

 levels with internal comparators

Supports dynamic host-peripheral switch of role

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Software-configurable to operate as:

SRP capable USB FS peripheral (B-device)

SRP capable USB FS/LS host (A-device)

USB On-The-Go Full-Speed dual role device

Supports FS SOF and LS keep-alives with

SOF pulse PAD connectivity

SOF pulse internal connection to timer (TIMx)

Configurable framing period

Configurable end of frame interrupt

USB 2.0 link power management (LPM) support

Includes power saving features such as system stop during USB suspend, switch-off 
of clock domains internal to the digital core, PHY, and DFIFO power management.

Dedicated RAM of 1.25 Kbytes with advanced FIFO control:

Configurable partitioning of RAM space into different FIFOs for flexible and 
efficient use of RAM

Each FIFO able to hold multiple packets

Dynamic memory allocation

Configurable FIFO sizes that are not powers of two to allow the use of contiguous 
memory locations

Max guaranteed USB bandwidth for up to one frame (1 ms) without system intervention

Support of charging port detection as described in

 Battery Charging Specification

 

revision 1.2 on the FS PHY transceiver only.

Host-mode features:

External charge pump for VBUS voltage generation.

Up to 12 host channels (pipes): each channel is dynamically reconfigurable to allocate 
any type of USB transfer.

Built-in hardware scheduler holding:

Up to 12 interrupt plus isochronous transfer requests in the periodic hardware 
queue

Up to 12 control plus bulk transfer requests in the nonperiodic hardware queue

Management of a shared Rx FIFO, a periodic Tx FIFO and a nonperiodic Tx FIFO for 
efficient usage of the USB data RAM

Peripheral-mode features:

1 bidirectional control endpoint0

5 IN endpoints (EPs) configurable to support bulk, interrupt, or isochronous transfers

5 OUT endpoints configurable to support bulk, interrupt, or isochronous transfers

Management of a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB 
data RAM

Management of up to 6 dedicated Tx-IN FIFOs (one for each active IN EP) to put less 
load on the application

Support for the soft disconnect feature

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3.48 

USB Type-C /USB Power Delivery controller (UCPD)

The device embeds one controller (UCPD) compliant with USB Type-C Cable and 
Connector Specification release 2.0 and USB Power Delivery Rev. 3.0 specifications.

The controller uses specific I/Os supporting the USB Type-C and USB power delivery 
requirements, featuring: 

USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors

“Dead battery” support

USB power delivery message transmission and reception

FRS (fast role swap) support

The digital controller handles notably:

USB Type-C level detection with debounce, generating interrupts

FRS detection, generating an interrupt

Byte-level interface for USB power delivery payload, generating interrupts 
(DMA compatible)

USB power delivery timing dividers (including a clock prescaler)

CRC generation/checking

4b5b encode/decode

Ordered sets (with a programmable ordered set mask at receive)

Frequency recovery in receiver during preamble

The interface offers low-power operation compatible with Stop mode, maintaining the 
capacity to detect incoming USB power delivery messages and FRS signaling.

3.49 Development 

support

3.49.1 Serial-wire/JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug 
port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can 
be reused as GPIO with alternate function): the JTAG TMS and TCK pins are shared with 
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to 
switch between JTAG-DP and SW-DP.

3.49.2 

Embedded Trace Macrocell

The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction 
and data flow inside the CPU core by streaming compressed data at a very high rate from 
the devices through a small number of ETM pins to an external hardware trace port analyzer 
(TPA) device. 

Real-time instruction and data flow activity be recorded and then formatted for display on 
the host computer that runs the debugger software. TPA hardware is commercially available 
from common development tool vendors.

The ETM operates with third party debugger software tools.

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Pinout, pin description and alternate functions

4.1 Pinout/ballout schematics

Figure 7. LQFP48_SMPS pinout

1. The above figure shows the package top view.

Figure 8. LQFP48 pinout

1. The above figure shows the package top view.

MSv62928V1

LQFP48

1

2

3

4

5

6

7

8

9

10

11

12

VBAT

PC13

PC14-OSC32_IN  

PC15-OSC32_OUT  

PH0-OSC_IN  

PH1-OSC_OUT  

NRST

VSSA

VDDA

PA0

PA1

PA2

36

35

34

33

32

31

30

29

28

27

26

25

39

37

40

38

45

43

41

48

47

46

44

42

22

24

21

23

16

18

20

13

14

15

17

19

PA

3

PA

4

PA

7

VLXSMPS

VSS

PA

5

PA

6

VDDSMPS

PB0

PB1

VSSSMPS

VDD1

1

VDD

VSS

PA13  

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

VDD

VDD

VSS

PH3-BOOT0

PB5

P

A14  

VDD1

1

PB8

PB4  

PB7

PB6

PB3  

P

A15  

MSv62922V1

LQFP48

1

2

3

4

5

6

7

8

9

10

11

12

VBAT

PC13

PC14-OSC32_IN  

PC15-OSC32_OUT  

PH0-OSC_IN  

PH1-OSC_OUT  

NRST

VSSA

VDDA

PA0

PA1

PA2

36

35

34

33

32

31

30

29

28

27

26

25

39

37

40

38

45

43

41

48

47

46

44

42

22

24

21

23

16

18

20

13

14

15

17

19

PA

3

PA

4

PA

7

PB2

VDD

PA

5

PA

6

PB10

PB0

PB1

VCAP

VSS

VDD

VSS

PA13  

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PH3-BOOT0

PB5

P

A14  

PB9

PB8

PB4  

PB7

PB6

PB3  

P

A15  

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Figure 9. UFQFPN48_SMPS pinout

1. The above figure shows the package top view.

Figure 10. UFQFPN48 pinout

1. The above figure shows the package top view.

MSv63695V3

UFQFPN48

1

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA

VDDA

PA0

PA1

PA2

36

35

34

33

32

31

30

29

28

27

26

25

39

37

40

38

45

43

41

48

47

46

44

42

22

24

21

23

16

18

20

13

14

15

17

19

PA

3

PA

4

PA

7

VLXSMPS

VSS

PA

5

PA

6

VDDSMPS

PB0

PB1

VSSSMPS

VDD1

1

VDD

VSS

PA13  

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

VDD

VDD

VSS

PH3-BOOT0

PB5

P

A14  

VDD1

1

PB8

PB4  

PB7

PB6

PB3  

P

A15  

2

3

4

5

6

7

8

9

10

11

12

MSv63696V2

UFQFPN48

1

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA

VDDA

PA0

PA1

PA2

36

35

34

33

32

31

30

29

28

27

26

25

39

37

40

38

45

43

41

48

47

46

44

42

22

24

21

23

16

18

20

13

14

15

17

19

PA

3

PA

4

PA

7

PB2

VDD

PA

5

PA

6

PB10

PB0

PB1

VCAP

VSS

VDD

VSS

PA13  

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PH3-BOOT0

PB5

P

A14  

PB9

PB8

PB4  

PB7

PB6

PB3  

P

A15  

2

3

4

5

6

7

8

9

10

11

12

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Figure 11. LQFP64_SMPS pinout

1. The above figure shows the package top view.

Figure 12. LQFP64 pinout

1. The above figure shows the package top view.

MSv62929V1

LQFP64

1

3

4

5

6

7

8

9

10

11

12

13

14

15

16

2

VBAT

48

46

45

44

43

42

41

40

39

38

37

36

35

34

33

47

55

53

52

51

50

49

56

54

61

59

57

64

63

62

60

58

26

28

29

30

31

32

25

27

20

22

24

17

18

19

21

23

PC13

PC15-OSC32_OUT  

PH1-OSC_OUT  

PC0

PC2

VSSA

PA0

PA1

PC14-OSC32_IN  

PH0-OSC_IN  

NRST

PC1

PC3

VDDA

PA2

VDDUSB

VSS

PA12

PA10

PA8

PC8

PC6

PB14

PB13

PA13  

PA11

PA9

PC9

PC7

PB15

VDD

PA

3

VSS

PA

4

PA

6

PB0

PB2

VLXSMPS

VSSSMPS

VDD1

1

VDD

PA

5

PA

7

PB1

PB10

VDDSMPS

VSS

VDD

VSS

PB8

PB7

PB5

PB3  

PC12

PC10

P

A15  

VDD1

1

PH3-BOOT0

PB6

PB4  

PD2

PC1

1

P

A14  

MSv62923V1

LQFP64

1

3

4

5

6

7

8

9

10

11

12

13

14

15

16

2

VBAT

48

46

45

44

43

42

41

40

39

38

37

36

35

34

33

47

55

53

52

51

50

49

56

54

61

59

57

64

63

62

60

58

26

28

29

30

31

32

25

27

20

22

24

17

18

19

21

23

PC13

PC15-OSC32_OUT  

PH1-OSC_OUT  

PC0

PC2

VSSA

PA0

PA1

PC14-OSC32_IN  

PH0-OSC_IN  

NRST

PC1

PC3

VDDA

PA2

VDDUSB

VSS

PA12

PA10

PA8

PC8

PC6

PB14

PB13

PA13  

PA11

PA9

PC9

PC7

PB15

PB12

PA

3

VSS

PA

4

PA

6

PC4

PB0

PB2

VCAP

VSS

VDD

PA

5

PA

7

PC5

PB1

PB10

VDD

VDD

VSS

PB8

PB7

PB5

PB3  

PC12

PC10

P

A15  

PB9

PH3-BOOT0

PB6

PB4  

PD2

PC1

1

P

A14  

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DS13737 Rev 10

Figure 13. WLCSP90_SMPS ballout

1. The above figure shows the package top view.

MSv62645V2

A

B

C

D

E

F

G

H

J

1

3

13

11

9

7

5

17

15

4

14

12

10

8

6

18

16

2

K

VSS

PC12

PD5

PG12

VSS

PB7

PB8

VSS

VDD

VDDUSB

PA14  

PD0

PG9

PG13

PB4  

PH3-BOOT0

PE3

VBAT

PA10

PA11

PA15  

PC10

PG11

PA9

PE5

PC13

PC15-

OSC32_OUT  

PC8

PC7

PC9

PA8

PA6

PC0

PD14

PD15

PB15

PC6

PC5

PA0

PC3

NRST

PA12

PA13  

PD1

PD4

PB3  

PB5

PE4

PC14-OSC32

_IN  

VDD

VSS

VSS

SMPS

PE10

PE8

PB1

PA1

VDDA

PB13

PB14

PB10

PE7

PA3

PA4

VREF+

VSSA

PC2

VDD

PC11

PD2

PG10

PG14

VDDIO2

PB6

PB9

VDD11

PE6

PH1-OSC_

OUT  

PH0-OSC_IN  

PC1

PA5

PA2

VDD11

VDD

SMPS

VLX

SMPS

PE9

PB2

PA7

VDD

VSS

PB0

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Figure 14. LQFP100_SMPS pinout

1. The above figure shows the package top view.

MSv62930V1

LQFP100

10

12

13

14

15

16

17

18

19

20

21

22

23

24

25

9

11

4

6

8

1

2

3

5

7

66

64

63

62

61

60

59

58

57

56

55

54

53

52

51

67

65

72

70

68

75

74

73

71

69

91

89

88

87

86

85

84

83

82

81

80

79

78

77

76

92

90

97

95

93

100

99

98

96

94

35

37

38

39

40

41

42

43

44

45

46

47

48

49

50

34

36

29

31

33

26

27

28

30

32

PE2

PE3

PE4

PE6

PC13

PC15-OSC32_OUT  

VDD

NRST

PC2

PE5

VBAT

PC14-OSC32_IN  

VSS

PH1-OSC_OUT  

PC1

VSSA

PA0

PA2

PH0-OSC_IN  

PC0

PC3

VREF+

PA1

PA3

VDDA

VDD

VSS

VDDUSB

PA12

PA10

PA8

PC8

PD15

PD12

PA13  

PA11

PA9

PC9

PC6

PD13

PD10

PB15

PB13

PC7

PD14

PD11

PD9

PB14

VDD

PD8

VSS

VDD

PA

4

PA

6

PB0

PB2

PE8

PE1

1

PE14

PA

5

PA

7

PB1

PE7

PE10

PE13

PB10

VDDSMPS

VDD1

1

PE9

PE12

PE15

PB1

1

VSSSMPS

VSS

VLXSMPS

VDD

VSS

VDD1

1

PB9

PH3-BOOT0

PB6

PB4  

PD6

PD3

PE0

PB8

PB7

PB5

PD7

PD4

PD1

PC1

1

P

A15  

PB3  

PD5

PD2

PD0

PC10

P

A14  

PC12

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Figure 15. LQFP100 pinout

1. The above figure shows the package top view.

MSv62924V1

LQFP100

10

12

13

14

15

16

17

18

19

20

21

22

23

24

25

9

11

4

6

8

1

2

3

5

7

66

64

63

62

61

60

59

58

57

56

55

54

53

52

51

67

65

72

70

68

75

74

73

71

69

91

89

88

87

86

85

84

83

82

81

80

79

78

77

76

92

90

97

95

93

100

99

98

96

94

35

37

38

39

40

41

42

43

44

45

46

47

48

49

50

34

36

29

31

33

26

27

28

30

32

PE2

PE3

PE4

PE6

PC13

PC15-OSC32_OUT  

VDD

NRST

PC2

PE5

VBAT

PC14-OSC32_IN  

VSS

PH1-OSC_OUT  

PC1

VSSA

VDDA

PA1

PH0-OSC_IN  

PC0

PC3

VREF-

PA0

PA2

VREF+

VDD

VSS

VDDUSB

PA12

PA10

PA8

PC8

PD15

PD12

PA13  

PA11

PA9

PC9

PC6

PD13

PD10

PB15

PB13

PC7

PD14

PD11

PD9

PB14

PB12

PD8

PA

3

VSS

VDD

PA

5

PA

7

PC5

PB1

PE8

PE1

1

PA

4

PA

6

PC4

PB0

PE7

PE10

PE13

PB10

VSS

PB2

PE9

PE12

PE14

VCAP

VDD

PE15

VDD

VSS

PE1

PB9

PH3-BOOT0

PB6

PB4  

PD6

PD3

PE0

PB8

PB7

PB5

PD7

PD4

PD1

PC1

1

P

A15  

PB3  

PD5

PD2

PD0

PC10

P

A14  

PC12

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Figure 16. UFBGA132_SMPS ballout

1. The above figure shows the package top view.

MSv62931V2

A

B

C

D

E

F

G

H

J

K

L

M

1

4

3

12

11

10

9

8

7

6

5

2

PA5

PA3

VDDA

VREF+

VSSA

PH1-OSC

_OUT  

PH0-

OSC_IN  

PF2

PC15-

OSC32_

OUT  

PC14-

OSC32

_IN  

VBAT

PE5

OPAMP2

_VINM

PA6

PA2

PA0

PC0

NRST

PF5

PF1

PF0

PE6

PE4

PE3

PC4

PA4

PA7

PC5

OPAMP1

_VINM

PC1

PC2

PF4

PF3

PC13

PE2

PE1

PB0

PB1

PB2

VDD

VSS

PA1

PC3

VSS

VDD

PE0

VDD11

PB9

PF13

PB7

PB8

PH3-

BOOT0

PB6

PG0

PG1

PE8

VDD

VSS

PB5

PB3  

PB4  

PG12

PE9

PE7

PE10

VSS

VDD

PD7

PG10

PG9

PD6

PE13

PE14

PE12

VDDIO2

PD3

PD4

PD5

VDD

SMPS

PB10

VDD

VSS

PG4

PG6

VDD

PD0

PD1

PD2

VLX

SMPS

PB13

PD9

PD14

PG2

PG7

PA9

PA13  

PC12

PC11

VDD11

PA10

PA14  

PC10

PA15  

PD10

PD8

PB15

PD12

PD15

PG5

PG8

PC8

PA8

PA11

PA12

VDDUSB

VSS

PC7

PC9

PC6

PG3

PD13

PD11

PB14

PF12

PF11

PF14

PF15

PE11

PE15

PB11

VSS

SMPS

PB12

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DS13737 Rev 10

Figure 17. UFBGA132 ballout

1. The above figure shows the package top view.

MSv62925V2

A

B

C

D

E

F

G

H

J

K

L

M

1

4

3

12

11

10

9

8

7

6

5

2

PA5

PA3

VDDA

VREF+

VSSA

PH1-

OSC_

OUT  

PH0-

OSC_IN  

PF2

PC15-

OSC32_

OUT  

PC14-

OSC32

_IN  

VBAT

PE5

OPAMP2

_VINM

PA6

PA2

PA0

PC0

NRST

PF5

PF1

PF0

PE6

PE4

PE3

PC4

PA4

PA7

PC5

OPAMP1

_VINM

PC1

PC2

PF4

PF3

PC13

PE2

PE1

PB0

PB1

PB2

VDD

VSS

PA1

PC3

VSS

VDD

PE0

PG15

PB9

PF13

PB7

PB8

PH3-

BOOT0

PB6

PG0

PG1

PE8

VDD

VSS

PB5

PB3  

PB4  

PG12

PE9

PE7

PE10

VSS

VDD

PD7

PG10

PG9

PD6

PE13

PE14

PE12

VDDIO2

PD3

PD4

PD5

PG14

PB10

VDD

VSS

PG4

PG6

VDD

PD0

PD1

PD2

PG13

PB13

PD9

PD14

PG2

PG7

PA9

PA13  

PC12

PC11

PG11

PA10

PA14  

PC10

PA15  

PD10

PD8

PB15

PD12

PD15

PG5

PG8

PC8

PA8

PA11

PA12

VDDUSB

VSS

PC7

PC9

PC6

PG3

PD13

PD11

PB14

PF12

PF11

PF14

PF15

PE11

PE15

PB11

VCAP

PB12

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149

Figure 18. LQFP144_SMPS pinout

1. The above figure shows the package top view.

MSv62932V1

LQFP144

23
24
25
26
27
28
29
30
31
32
33
34
35
36

20

22

15

17

19

13
14

16

18

88

86
85
84
83
82
81
80
79
78
77
76
75
74
73

89

87

94

92

90

97
96
95

93

91

135

133

132

131

130

129

128

127

126

125

124

123

122

121

136

134

141

139

137

144

143

142

140

138

47

49

50

51

52

53

54

55

56

57

58

59

60

61

72

46

48

41

43

45

38

39

40

42

44

120

11

9

11

8

11

7

11

6

11

5

11

4

11

3

11

2

111

11

0

109

108

VDD

104

107
106
105

103

99
98

101
100

102

68

69

70

71

64

65

66

67

62

63

37

12

11

6

8

10

4
5

7

9

3

2

1

PE2

21

PC13

PC15-OSC32_OUT  

PF1

PF3

PF5

VDD

PF7

PF9

PH0-OSC_IN  

NRST

PC1

PC3

VREF+

PA0

PA2

PE3

PE5

PC14-OSC32_IN  

PF0

PF2

PF4

VSS

PF6

PF8

PF10

PH1-OSC_OUT  

PC0

PC2

VSSA

VDDA

PA1

PA3

PE4

VBAT

PE6

PA10

PA8

PC8

PC6

VSS

PG7

PG5

PG3

PD15

VDD

PD13

PD11

PD9

PB15

PB13

VSS

PA13  

PA9

PC9

PC7

VDDIO2

PG8

PG6

PG4

PG2

PD14

VSS

PD12

PD10

PD8

PB14

VDD

VDDUSB

PA11

PA12

VDD

PB8

PB7

PB5

PB3  

VDDIO2

PG14

PG12

PG9

PD6

VSS

PD4

PD2

PD0

PC1

1

P

A15  

VSS

PE1

PH3-BOOT0

PB6

PB4  

PG15

VSS

PG13

PG10

PD7

VDD

PD5

PD3

PD1

PC12

PC10

P

A14  

VDD1

1

PB9

PE0

VSS

PB0

PB2

PF12

VDD

PF14

PG0

PE7

PE9

VDD

PE1

1

PE13

PE15

PB1

1

VDDSMPS

VDD1

1

VDD

PA

5

PB1

PF1

1

VSS

PF13

PF15

PG1

PE8

VSS

PE10

PE12

PE14

PB10

VLXSMPS

VSSSMPS

VSS

PA

4

PA

7

PA

6

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STM32U575xx

100/346

DS13737 Rev 10

Figure 19. LQFP144 pinout

1. The above figure shows the package top view.

MSv62926V1

LQFP144

23
24
25
26
27
28
29
30
31
32
33
34
35
36

20

22

15

17

19

13
14

16

18

88

86
85
84
83
82
81
80
79
78
77
76
75
74
73

89

87

94

92

90

97
96
95

93

91

135

133

132

131

130

129

128

127

126

125

124

123

122

121

136

134

141

139

137

144

143

142

140

138

47

49

50

51

52

53

54

55

56

57

58

59

60

61

72

46

48

41

43

45

38

39

40

42

44

120

11

9

11

8

11

7

11

6

11

5

11

4

11

3

11

2

111

11

0

109

108

VDD

104

107
106
105

103

99
98

101
100

102

68

69

70

71

64

65

66

67

62

63

37

12

11

6

8

10

4
5

7

9

3

2

1

PE2

21

PC13

PC15-OSC32_OUT  

PF1

PF3

PF5

VDD

PF7

PF9

PH0-OSC_IN  

NRST

PC1

PC3

VREF-

VDDA

PA1

PE3

PE5

PC14-OSC32_IN  

PF0

PF2

PF4

VSS

PF6

PF8

PF10

PH1-OSC_OUT  

PC0

PC2

VSSA

VREF+

PA0

PA2

PE4

VBAT

PE6

PA10

PA8

PC8

PC6

VSS

PG7

PG5

PG3

PD15

VDD

PD13

PD11

PD9

PB15

PB13

VSS

PA13  

PA9

PC9

PC7

VDDIO2

PG8

PG6

PG4

PG2

PD14

VSS

PD12

PD10

PD8

PB14

PB12

VDDUSB

PA11

PA12

VDD

PH3-BOOT0

PB6

PB4  

PG15

VSS

PG13

PG1

1

PG9

PD6

VSS

PD4

PD2

PD0

PC1

1

P

A15  

VSS

PE0

PB7

PB5

PB3  

VDDIO2

PG14

PG12

PG10

PD7

VDD

PD5

PD3

PD1

PC12

PC10

P

A14  

PE1

PB8

PB9

PA

3

PA

7

PC5

PB1

PF1

1

VSS

PF13

PF15

PG1

PE8

VSS

PE10

PE12

PE14

PB10

VSS

VSS

PA

4

PC4

PB0

PB2

PF12

VDD

PF14

PG0

PE7

PE9

VDD

PE1

1

PE13

PE15

VCAP

VDD

VDD

PA

6

PA

5

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STM32U575xx

Pinout, pin description and alternate functions

149

Figure 20. UFBGA169_SMPS ballout

1. The above figure shows the package top view.

MSv62933V3

A

B

C

D

E

F

G

H

J

K

L

M

N

1

4

3

13

12

11

10

9

8

7

6

5

2

PA4

OPAMP1

_VINM

VREF+

PC3

PH1-

OSC_

OUT  

PH0-

OSC_IN  

VDD

PF8

PC15-

OSC32_

OUT  

PC14-

OSC32

_IN  

VBAT

VDD

PE2

PA3

PA2

VDDA

VSSA

PC0

VSS

PF7

VSS

PF0

PE5

PE4

VSS

PI6

VDD

VSS

PA1

PA0

PC1

NRST

PF9

PF1

PC13

PE3

PI7

PI5

VDD

PA6

PC5

PC4

PA5

PC2

PF10

PF5

PF2

PE6

PE0

PE1

VSS

VDD11

PB1

PF11

PB9

PH3-

BOOT0

PB6

PG15

PF15

PF13

PF12

PG0

PF6

PF4

PD1

PB3  

PB5

PB4  

VDDIO2

VDD

VSS

PE8

PD2

PD7

PG10

PD6

PG9

PE12

PE11

PE14

PH7

PD3

PD4

VSS

VDD

VLX

SMPS

PE15

PB10

PH5

PH11

PC10

PD0

PC11

VDD

SMPS

VSS

SMPS

PD12

PD14

PG6

PC8

PH2

PI3

PA14  

PI4

PA15  

VDD11

VSS

PI2

PH14

VSS

VDD

VDD

PB14

PD8

PD13

VSS

VDDIO2

PC7

PA13  

VSS

PH8

PH13

PI0

PI1

PB13

PD11

PD9

PG2

VDD

PC6

PA11

PA12

VDDUSB

VDD

PH10

PH12

PH15

PB8

PG12

PD5

PC12

PH9

PH4

PH6

PB7

PA10

PF3

PA9

PG4

PB15

PD10

PD15

PB2

PB0

PA7

OPAMP2

_VINM

PF14

PE7

PE13

PB11

PB12

PE9

PG1

PA8

PG3

PE10

PG7

PG5

PG8

PC9

STM32U575RGT6-html.html

Pinout, pin description and alternate functions

STM32U575xx

102/346

DS13737 Rev 10

Figure 21. UFBGA169 ballout

1. The above figure shows the package top view.

MSv62927V3

A

B

C

D

E

F

G

H

J

K

L

M

N

1

4

3

13

12

11

10

9

8

7

6

5

2

PA4

OPAMP1

_VINM

VREF+

PC3

PH1-

OSC_

OUT  

PH0-

OSC_IN  

VDD

PF8

PC15-

OSC32_

OUT  

PC14-

OSC32_

IN  

VBAT

VDD

PE2

PA3

PA2

VDDA

VSSA

PC0

VSS

PF7

VSS

PF0

PE5

PE4

VSS

PI6

VDD

VSS

PA1

PA0

PC1

NRST

PF9

PF1

PC13

PE3

PI7

PI5

VDD

PA6

PC5

PC4

PA5

PC2

PF10

PF5

PF2

PE6

PE0

PE1

VSS

VCAP

PB1

PF11

PB9

PH3-

BOOT0

PB6

PG15

PF15

PF13

PF12

PG0

PF6

PF4

PD1

PB3  

PB5

PB4  

VDDIO2

VDD

VSS

PE8

PD2

PD7

PG10

PD6

PG9

PE12

PE11

PE14

PH7

PD3

PD4

VSS

VDD

PG14

PE15

PB10

PH5

PH11

PC10

PD0

PC11

PG13

PG11

PD12

PD14

PG6

PC8

PH2

PI3

PA14  

PI4

PA15  

VCAP

VSS

PI2

PH14

VSS

VDD

VDD

PB14

PD8

PD13

VSS

VDDIO2

PC7

PA13  

VSS

PH8

PH13

PI0

PI1

PB13

PD11

PD9

PG2

VDD

PC6

PA11

PA12

VDDUSB

VDD

PH10

PH12

PH15

PB8

PG12

PD5

PC12

PH9

PH4

PH6

PB7

PA10

PF3

PA9

PG4

PB15

PD10

PD15

PB2

PB0

PA7

OPAMP2

_VINM

PF14

PE7

PE13

PB11

PB12

PE9

PG1

PA8

PG3

PE10

PG7

PG5

PG8

PC9

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STM32U575xx

Pinout, pin description and alternate functions

149

4.2 Pin 

description

          

Table 25. Legend/abbreviations used in the pinout table 

Name

Abbreviation

Definition

Pin name

Unless otherwise specified in brackets below the pin name, the pin function during 

and after reset is the same as the actual pin name

Pin type

S

Supply pin

I

Input only pin

I/O

Input/output pin

I/O structure

FT

5V-tolerant I/O

TT

3.6V-tolerant I/O

RST

Bidirectional reset pin with embedded weak pull-up 
resistor

Option for TT or FT I/Os

(1)

_a

I/O, with analog switch function supplied by V

DDA

_c

I/O with USB Type-C power delivery function

_d

I/O with USB Type-C power delivery dead battery function

_f

I/O, Fm+ capable

_h

I/O with high-speed low-voltage mode

_o

I/O with OSC32_IN/OSC32_OUT capability

_s

I/O supplied only by V

DDIO2

_t

I/O with a function supplied by V

SW

_u

I/O, with USB function supplied by V

DDUSB

_v

I/O very high-speed capable

Notes

Unless otherwise specified by a note, all I/Os are set as analog inputs during and after 
reset.

Pin 

functions

Alternate 
functions

Functions selected through GPIOx_AFR registers

Additional 

functions

Functions directly selected/enabled through peripheral registers

1. The related I/O structures in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u, TT_a.

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

04/346

DS137

37 Rev 10

          

Table 26. STM32U575xx pin definitions

(1)

 

Pin number

Pin name 

(function after 

reset)

Pi

n t

yp

e

I/

O structure

No

te

s

Alternate functions

Additional 

functions

LQFP

48 S

M

PS

UF

QF

PN48 S

M

PS

LQFP

64 S

M

PS

WLC

S

P90

 S

M

PS

LQ

FP

100 S

M

PS

UFBGA

132 S

M

PS

LQ

FP

144 S

M

PS

UFBGA

169 S

M

PS

LQF

P

48

UF

Q

F

P

N

48

LQF

P

64

LQFP

100

UF

BG

A

132

LQFP

144

UF

BG

A

169

-

-

-

1

B3

1

A1

-

-

1

B3

1

A1

PE2

I/O FT_ha

-

TRACECLK, TIM3_ETR, 

SAI1_CK1, TSC_G7_IO1, 

LPGPIO1_P14, FMC_A23, 

SAI1_MCLK_A, EVENTOUT

-

-

-

C15

2

A2

2

D3

-

-

2

A2

2

D3

PE3

I/O

FT_

hat

-

TRACED0, TIM3_CH1, 

OCTOSPIM_P1_DQS, 

TSC_G7_IO2, LPGPIO1_P15, 

FMC_A19, SAI1_SD_B, 

EVENTOUT

TAMP_IN6/

TAMP_

OUT3

-

-

D14

3

B2

3

C2

-

-

3

B2

3

C2

PE4

I/O

FT_

hat

-

TRACED1, TIM3_CH2, SAI1_D2, 

MDF1_SDI3, TSC_G7_IO3, 

DCMI_D4/PSSI_D4, FMC_A20, 

SAI1_FS_A, EVENTOUT

WKUP1, 

TAMP_IN7/

TAMP_

OUT8

-

-

E13

4

A1

4

D2

-

-

4

A1

4

D2

PE5

I/O

FT_

hat

-

TRACED2, TIM3_CH3, 

SAI1_CK2, MDF1_CKI3, 

TSC_G7_IO4, 

DCMI_D6/PSSI_D6, FMC_A21, 

SAI1_SCK_A, EVENTOUT

WKUP2, 

TAMP_IN8/

TAMP_

OUT7

-

-

D16

5

C2

5

E4

-

-

5

C2

5

E4

PE6

I/O FT_ht

-

TRACED3, TIM3_CH4, SAI1_D1, 

DCMI_D7/PSSI_D7, FMC_A22, 

SAI1_SD_A, EVENTOUT

WKUP3, 

TAMP_IN3/

TAMP_

OUT6

1

1

C17

6

B1

6

C1

1

1

6

B1

6

C1

VBAT

S

-

-

-

-

-

-

-

-

-

-

F2

-

-

-

-

-

F2

VSS

S

-

-

-

-

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

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rip
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d alter

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e fu

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io

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1

05/346

2

2

E15

7

C3

7

E3

2

2

7

C3

7

E3

PC13

I/O

FT

(2)

 

(3)

EVENTOUT

WKUP2, 

RTC_TS/

RTC_OUT1, 

TAMP_IN1/

TAMP_

OUT2

3

3

D18

8

C1

8

D1

3

3

8

C1

8

D1

PC14-

OSC32_IN 

(PC14)

I/O

FT_o

(2)
(3)

EVENTOUT

OSC32_IN

4

4

E17

9

D1

9

E1

4

4

9

D1

9

E1

PC15-

OSC32_OUT 

(PC15)

I/O

FT_o

(2)
(3)

EVENTOUT

OSC32_

OUT

-

-

-

-

D2

10

E2

-

-

-

D2

10

E2

PF0

I/O FT_fh

-

I2C2_SDA, OCTOSPIM_P2_IO0, 

FMC_A0, EVENTOUT

-

-

-

-

-

E2

11

F3

-

-

-

E2

11

F3

PF1

I/O FT_fh

-

I2C2_SCL, OCTOSPIM_P2_IO1, 

FMC_A1, EVENTOUT

-

-

-

-

-

E1

12

F4

-

-

-

E1

12

F4

PF2

I/O

FT_h

-

LPTIM3_CH2, I2C2_SMBA, 

OCTOSPIM_P2_IO2, FMC_A2, 

EVENTOUT

WKUP8

-

-

-

-

D3

13

G5

-

-

-

D3

13

G5

PF3

I/O

FT_h

-

LPTIM3_IN1, 

OCTOSPIM_P2_IO3, FMC_A3, 

EVENTOUT

-

-

-

-

-

E3

14

G6

-

-

-

E3

14

G6

PF4

I/O FT_hv

-

LPTIM3_ETR, 

OCTOSPIM_P2_CLK, FMC_A4, 

EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
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e

rna
te

 func
tions

ST
M32

U

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5x

x

1

06/346

DS137

37 Rev 10

-

-

-

-

F2

15

G4

-

-

-

F2

15

G4

PF5

I/O FT_hv

-

LPTIM3_CH1, 

OCTOSPIM_P2_NCLK, FMC_A5, 

EVENTOUT

-

-

-

-

10

F6

16

H2

-

-

10

F6

16

H2

VSS

S

-

-

-

-

-

-

-

11

F7

17

G1

-

-

11

F7

17

G1

VDD

S

-

-

-

-

-

-

-

-

-

18

H6

-

-

-

-

18

H6

PF6

I/O

FT_h

-

TIM5_ETR, TIM5_CH1, 

DCMI_D12/PSSI_D12, 

OCTOSPIM_P2_NCS, 

OCTOSPIM_P1_IO3, 

SAI1_SD_B, EVENTOUT

-

-

-

-

-

-

19

G2

-

-

-

-

19

G2

PF7

I/O

FT_h

-

TIM5_CH2, FDCAN1_RX, 

OCTOSPIM_P1_IO2, 

SAI1_MCLK_B, EVENTOUT

-

-

-

-

-

-

20

F1

-

-

-

-

20

F1

PF8

I/O

FT_h

-

TIM5_CH3, PSSI_D14, 

FDCAN1_TX, 

OCTOSPIM_P1_IO0, 

SAI1_SCK_B, EVENTOUT

-

-

-

-

-

-

21

G3

-

-

-

-

21

G3

PF9

I/O

FT_h

-

TIM5_CH4, PSSI_D15, 

OCTOSPIM_P1_IO1, 

SAI1_FS_B, TIM15_CH1, 

EVENTOUT

-

-

-

-

-

-

22

H4

-

-

-

-

22

H4

PF10

I/O FT_hv

-

OCTOSPIM_P1_CLK, PSSI_D15, 

MDF1_CCK1, 

DCMI_D11/PSSI_D11, SAI1_D3, 

TIM15_CH2, EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

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e fu

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DS137

37 Rev 10

1

07/346

5

5

F18

12

F1

23

H1

5

5

12

F1

23

H1

PH0-OSC_IN 

(PH0)

I/O

FT

-

EVENTOUT

OSC_IN

6

6

F16

13

G1

24

J1

6

6

13

G1

24

J1

PH1-OSC_OUT 

(PH1)

I/O

FT

-

EVENTOUT

OSC_OUT

7

7

G17

14

G2

25

H3

7

7

14

G2

25

H3

NRST

I/O

RST

-

-

-

-

8

F14

15

H2

26

J2

-

8

15

H2

26

J2

PC0

I/O

FT_

fha

-

LPTIM1_IN1, 

OCTOSPIM_P1_IO7, 

I2C3_SCL(boot), SPI2_RDY, 
MDF1_SDI4, LPUART1_RX, 

SDMMC1_D5, SAI2_FS_A, 

LPTIM2_IN1, EVENTOUT

ADC1_IN1, 

ADC4_IN1

-

9

G15

16

G3

27

J3

-

9

16

G3

27

J3

PC1

I/O

FT_

fhav

-

TRACED0, LPTIM1_CH1, 

SPI2_MOSI, I2C3_SDA(boot), 

MDF1_CKI4, LPUART1_TX, 

OCTOSPIM_P1_IO4, 

SDMMC2_CK, SAI1_SD_A, 

EVENTOUT

ADC1_IN2, 

ADC4_IN2

-

10

F12

17

F3

28

J4

-

10

17

F3

28

J4

PC2

I/O FT_ha

-

LPTIM1_IN2, SPI2_MISO, 

MDF1_CCK1, 

OCTOSPIM_P1_IO5, 

LPGPIO1_P5, EVENTOUT

ADC1_IN3, 

ADC4_IN3

-

11

G13

18

F4

29

K1

-

11

18

F4

29

K1

PC3

I/O FT_ha

-

LPTIM1_ETR, LPTIM3_CH1, 

SAI1_D1, SPI2_MOSI, 

OCTOSPIM_P1_IO6, 

SAI1_SD_A, LPTIM2_ETR, 

EVENTOUT

ADC1_IN4, 

ADC4_IN4

8

12

H18

19

H1

30

K2

8

12

19

H1

30

K2

VSSA

S

-

-

-

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

08/346

DS137

37 Rev 10

-

-

-

-

-

-

-

-

-

20

-

31

-

VREF-

S

-

-

-

-

-

-

H16

20

J1

31

L1

-

-

21

J1

32

L1

VREF+

S

-

-

-

VREFBUF_

OUT

9

13

J17

21

K1

32

L2

9

13

22

K1

33

L2

VDDA

S

-

-

-

-

10

14

G11

22

J2

33

K3

10

14

23

J2

34

K3

PA0

I/O

FT_

hat

-

TIM2_CH1, TIM5_CH1, 

TIM8_ETR, SPI3_RDY, 

USART2_CTS, UART4_TX, 

OCTOSPIM_P2_NCS, 

SDMMC2_CMD, AUDIOCLK, 

TIM2_ETR, EVENTOUT

OPAMP1_

VINP, 

ADC1_IN5, 

WKUP1, 

TAMP_IN2/

TAMP_

OUT1

-

-

-

-

H3

-

M1

-

-

-

H3

-

M1

OPAMP1_

VINM

I

TT

-

-

-

11

15

J13

23

G4

34

L3

11

15

24

G4

35

L3

PA1

I/O

FT_

hat

-

LPTIM1_CH2, TIM2_CH2, 

TIM5_CH2, I2C1_SMBA, 

SPI1_SCK, 

USART2_RTS/USART2_DE, 

UART4_RX, 

OCTOSPIM_P1_DQS, 

LPGPIO1_P0, TIM15_CH1N, 

EVENTOUT

OPAMP1_

VINM, 

ADC1_IN6, 

WKUP3, 

TAMP_IN5/

TAMP_

OUT4

12

16

J15

24

K2

35

M2

12

16

25

K2

36

M2

PA2

I/O FT_ha

-

TIM2_CH3, TIM5_CH3, 

SPI1_RDY, USART2_TX(boot), 

LPUART1_TX, 

OCTOSPIM_P1_NCS, 

UCPD1_FRSTX1, TIM15_CH1, 

EVENTOUT

COMP1_

INP3, 

ADC1_IN7, 

WKUP4/

LSCO

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

1

09/346

13

17

H10

25

L1

36

N2

13

17

26

L1

37

N2

PA3

I/O

TT_

hav

-

TIM2_CH4, TIM5_CH4, 

SAI1_CK1, USART2_RX(boot), 

LPUART1_RX, 

OCTOSPIM_P1_CLK, 

LPGPIO1_P1, SAI1_MCLK_A, 

TIM15_CH2, EVENTOUT

OPAMP1_

VOUT, 

ADC1_IN8, 

WKUP5

-

18

K18

26

G7

37

M3

-

18

27

G7

38

M3

VSS

S

-

-

-

-

-

19

K16

27

G6

38

N3

-

19

28

G6

39

N3

VDD

S

-

-

-

-

14

20

H14

28

L3

39

N1

14

20

29

L3

40

N1

PA4

I/O TT_ha

-

OCTOSPIM_P1_NCS, 

SPI1_NSS(boot), SPI3_NSS, 

USART2_CK, 

DCMI_HSYNC/PSSI_DE, 

SAI1_FS_B, LPTIM2_CH1, 

EVENTOUT

ADC1_IN9, 
ADC4_IN9, 

DAC1_

OUT1, 

WKUP2

15

21

H12

29

M1

40

K4

15

21

30

M1

41

K4

PA5

I/O

TT_a

-

CSLEEP, TIM2_CH1, TIM2_ETR, 

TIM8_CH1N, PSSI_D14, 

SPI1_SCK(boot), USART3_RX, 

LPTIM2_ETR, EVENTOUT

ADC1_IN10, 
ADC4_IN10, 

DAC1_

OUT2, 

WKUP6

16

22

F10

30

L2

41

N4

16

22

31

L2

42

N4

PA6

I/O FT_ha

-

CDSTOP, TIM1_BKIN, 

TIM3_CH1, TIM8_BKIN, 

DCMI_PIXCLK/PSSI_PDCK, 

SPI1_MISO(boot), 

USART3_CTS, LPUART1_CTS, 

OCTOSPIM_P1_IO3, 

LPGPIO1_P2, TIM16_CH1, 

EVENTOUT

OPAMP2_

VINP, 

ADC1_IN11, 
ADC4_IN11, 

WKUP7

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

11

0/346

DS137

37 Rev 10

-

-

-

-

M2

-

H5

-

-

-

M2

-

H5

OPAMP2_VINM

I

TT

-

-

-

17

23

K14

31

K3

42

J5

17

23

32

K3

43

J5

PA7

I/O

FT_

fha

-

SRDSTOP, TIM1_CH1N, 

TIM3_CH2, TIM8_CH1N, 

I2C3_SCL, SPI1_MOSI(boot), 

USART3_TX, 

OCTOSPIM_P1_IO2, 

LPTIM2_CH2, TIM17_CH1, 

EVENTOUT

OPAMP2_

VINM, 

ADC1_IN12, 
ADC4_IN20, 

WKUP8

-

-

-

-

M3

-

L4

-

24

33

M3

44

L4

PC4

I/O FT_ha

-

USART3_TX, 

OCTOSPIM_P1_IO7, 

EVENTOUT

COMP1_

INM2, 

ADC1_IN13, 

ADC4_IN22

-

-

G9

-

J3

-

M4

-

25

34

J3

45

M4

PC5

I/O FT_at

-

TIM1_CH4N, SAI1_D3, 

PSSI_D15, USART3_RX, 

EVENTOUT

COMP1_

INP1, 

ADC1_IN14, 
ADC4_IN23, 

WKUP5, 

TAMP_IN4/

TAMP_

OUT5

18

24

K12

32

M4

43

K5

18

26

35

M4

46

K5

PB0

I/O TT_ha

-

TIM1_CH2N, TIM3_CH3, 

TIM8_CH2N, LPTIM3_CH1, 

SPI1_NSS, USART3_CK, 

OCTOSPIM_P1_IO1, 

LPGPIO1_P9, COMP1_OUT, 

AUDIOCLK, EVENTOUT

OPAMP2_

VOUT, 

ADC1_IN15, 

ADC4_IN18

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

11

1/346

19

25

J11

33

L4

44

N5

19

27

36

L4

47

N5

PB1

I/O FT_ha

-

TIM1_CH3N, TIM3_CH4, 

TIM8_CH3N, LPTIM3_CH2, 

MDF1_SDI0, 

USART3_RTS/USART3_DE, 

LPUART1_RTS/LPUART1_DE, 

OCTOSPIM_P1_IO0, 

LPGPIO1_P3, LPTIM2_IN1, 

EVENTOUT

COMP1_

INM1, 

ADC1_IN16, 
ADC4_IN19, 

WKUP4

-

26

K10

34

K4

45

L5

20

28

37

K4

48

L5

PB2

I/O

FT_

hat

-

LPTIM1_CH1, TIM8_CH4N, 

I2C3_SMBA, SPI1_RDY, 

MDF1_CKI0, 

OCTOSPIM_P1_DQS, 

UCPD1_FRSTX1, EVENTOUT

COMP1_

INP2, 

ADC1_IN17, 

WKUP1, 

RTC_OUT2

-

-

-

-

K5

46

M5

-

-

-

K5

49

M5

PF11

I/O FT_hv

-

OCTOSPIM_P1_NCLK, 

DCMI_D12/PSSI_D12, 

LPTIM4_IN1, EVENTOUT

-

-

-

-

-

L5

47

K6

-

-

-

L5

50

K6

PF12

I/O

FT_h

-

OCTOSPIM_P2_DQS, FMC_A6, 

LPTIM4_ETR, EVENTOUT

-

-

-

-

-

-

48

M7

-

-

-

-

51

M7

VSS

S

-

-

-

-

-

-

-

-

-

49

N7

-

-

-

-

52

N7

VDD

S

-

-

-

-

-

-

-

-

M5

50

M6

-

-

-

M5

53

M6

PF13

I/O

FT_h

-

I2C4_SMBA, UCPD1_FRSTX2, 

FMC_A7, LPTIM4_OUT, 

EVENTOUT

-

-

-

-

-

J5

51

L6

-

-

-

J5

54

L6

PF14

I/O

FT_

fha

-

I2C4_SCL, TSC_G8_IO1, 

FMC_A8, EVENTOUT

ADC4_IN5

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

11

2/346

DS137

37 Rev 10

-

-

-

-

L6

52

N6

-

-

-

L6

55

N6

PF15

I/O

FT_

fha

-

I2C4_SDA, TSC_G8_IO2, 

FMC_A9, EVENTOUT

ADC4_IN6

-

-

-

-

M6

53

J6

-

-

-

M6

56

J6

PG0

I/O FT_ha

-

OCTOSPIM_P2_IO4, 

TSC_G8_IO3, FMC_A10, 

EVENTOUT

ADC4_IN7

-

-

-

-

K6

54

H7

-

-

-

K6

57

H7

PG1

I/O FT_ha

-

OCTOSPIM_P2_IO5, 

TSC_G8_IO4, FMC_A11, 

EVENTOUT

ADC4_IN8

-

-

H8

35

K7

55

L7

-

-

38

K7

58

L7

PE7

I/O

FT_h

-

TIM1_ETR, MDF1_SDI2, 

FMC_D4/FMC_AD4, SAI1_SD_B, 

EVENTOUT

WKUP6

-

-

J9

36

J6

56

K7

-

-

39

J6

59

K7

PE8

I/O

FT_h

-

TIM1_CH1N, MDF1_CKI2, 

FMC_D5/FMC_AD5, 

SAI1_SCK_B, EVENTOUT

WKUP7

-

-

K8

37

M7

57

J7

-

-

40

M7

60

J7

PE9

I/O FT_hv

-

TIM1_CH1, ADF1_CCK0, 

MDF1_CCK0, 

OCTOSPIM_P1_NCLK, 

FMC_D6/FMC_AD6, SAI1_FS_B, 

EVENTOUT

-

-

-

-

-

-

58

-

-

-

-

-

61

-

VSS

S

-

-

-

-

-

-

-

-

J4

59

-

-

-

-

J4

62

-

VDD

S

-

-

-

-

-

-

J7

38

J7

60

H8

-

-

41

J7

63

H8

PE10

I/O

FT_

hav

-

TIM1_CH2N, ADF1_SDI0, 

MDF1_SDI4, TSC_G5_IO1, 

OCTOSPIM_P1_CLK, 

FMC_D7/FMC_AD7, 

SAI1_MCLK_B, EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

113/346

-

-

-

39

L7

61

M8

-

-

42

L7

64

M8

PE11

I/O FT_ha

-

TIM1_CH2, SPI1_RDY, 

MDF1_CKI4, TSC_G5_IO2, 

OCTOSPIM_P1_NCS, 

FMC_D8/FMC_AD8, EVENTOUT

-

-

-

-

40

J8

62

N8

-

-

43

J8

65

N8

PE12

I/O FT_ha

-

TIM1_CH3N, SPI1_NSS, 

MDF1_SDI5, TSC_G5_IO3, 

OCTOSPIM_P1_IO0, 

FMC_D9/FMC_AD9, EVENTOUT

-

-

-

-

41

M8

63

L8

-

-

44

M8

66

L8

PE13

I/O FT_ha

-

TIM1_CH3, SPI1_SCK, 

MDF1_CKI5, TSC_G5_IO4, 

OCTOSPIM_P1_IO1, 

FMC_D10/FMC_AD10, 

EVENTOUT

-

-

-

-

42

K8

64

K8

-

-

45

K8

67

K8

PE14

I/O

FT_h

-

TIM1_CH4, TIM1_BKIN2, 

SPI1_MISO, 

OCTOSPIM_P1_IO2, 

FMC_D11/FMC_AD11, 

EVENTOUT

-

-

-

-

43

L8

65

M9

-

-

46

L8

68

M9

PE15

I/O

FT_h

-

TIM1_BKIN, TIM1_CH4N, 

SPI1_MOSI, 

OCTOSPIM_P1_IO3, 

FMC_D12/FMC_AD12, 

EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

11

4/346

DS137

37 Rev 10

-

27

H6

44

K9

66

K9

21

29

47

K9

69

K9

PB10

I/O

FT_

fhv

-

TIM2_CH3, LPTIM3_CH1, 

I2C4_SCL, I2C2_SCL(boot), 

SPI2_SCK, USART3_TX, 

LPUART1_RX, TSC_SYNC, 

OCTOSPIM_P1_CLK, 

LPGPIO1_P4, COMP1_OUT, 

SAI1_SCK_A, EVENTOUT

WKUP8

-

-

-

45

L9

67

L9

-

-

-

L9

-

L9

PB11

I/O FT_fh

-

TIM2_CH4, I2C4_SDA, 

I2C2_SDA(boot), SPI2_RDY, 

USART3_RX, LPUART1_TX, 

OCTOSPIM_P1_NCS, 

COMP2_OUT, EVENTOUT

-

20

28

K6

46

M10

68

N9

-

-

-

-

-

-

VLXSMPS

S

-

-

-

-

21

29

K4

47

M9

69

N10

-

-

-

-

-

-

VDDSMPS

S

-

-

-

-

22

30

J5

48

L10

70

M10

-

-

-

-

-

-

VSSSMPS

S

-

-

-

-

-

-

-

-

-

-

-

22

30

48

L10

70

N11

VCAP

S

-

-

-

-

23

31

K2

49

M11

71

N11

-

-

-

-

-

-

VDD11

S

-

-

-

-

24

32

J3

50

E9

72

M11

23

31

49

E9

71

M11

VSS

S

-

-

-

-

25

33

J1

51

D4

73

N12

24

32

50

D4

72

N12

VDD

S

-

-

-

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

115/346

-

-

-

-

L11

-

L10

25

33

51

L11

73

L10

PB12

I/O

FT_

hav

-

TIM1_BKIN, I2C2_SMBA, 

SPI2_NSS(boot), MDF1_SDI1, 

USART3_CK, 

LPUART1_RTS/LPUART1_DE, 

TSC_G1_IO1, 

OCTOSPIM_P1_NCLK, 

SAI2_FS_A, TIM15_BKIN, 

EVENTOUT

-

26

34

H2

52

K10

74

N13

26

34

52

K10

74

N13

PB13

I/O FT_fa

-

TIM1_CH1N, LPTIM3_IN1, 

I2C2_SCL, SPI2_SCK(boot), 
MDF1_CKI1, USART3_CTS, 

LPUART1_CTS, TSC_G1_IO2, 

SAI2_SCK_A, TIM15_CH1N, 

EVENTOUT

-

27

35

H4

53

K11

75

M12

27

35

53

K11

75

M12

PB14

I/O

FT_

fda

-

TIM1_CH2N, LPTIM3_ETR, 

TIM8_CH2N, I2C2_SDA, 

SPI2_MISO(boot), MDF1_SDI2, 

USART3_RTS/USART3_DE, 

TSC_G1_IO3, SDMMC2_D0, 

SAI2_MCLK_A, TIM15_CH1, 

EVENTOUT

UCPD1_

DBCC2

28

36

G5

54

K12

76

L11

28

36

54

K12

76

L11

PB15

I/O

FT_c

(4)

RTC_REFIN, TIM1_CH3N, 
LPTIM2_IN2, TIM8_CH3N, 

SPI2_MOSI(boot), MDF1_CKI2, 

FMC_NBL1, SDMMC2_D1, 

SAI2_SD_A, TIM15_CH2, 

EVENTOUT

UCPD1_

CC2, 

WKUP7

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

11

6/346

DS137

37 Rev 10

-

-

-

55

L12

77

L12

-

-

55

L12

77

L12

PD8

I/O

FT_h

-

USART3_TX, 

DCMI_HSYNC/PSSI_DE, 

FMC_D13/FMC_AD13, 

EVENTOUT

-

-

-

-

56

J10

78

L13

-

-

56

J10

78

L13

PD9

I/O

FT_h

-

LPTIM2_IN2, USART3_RX, 

DCMI_PIXCLK/PSSI_PDCK, 

FMC_D14/FMC_AD14, 

SAI2_MCLK_A, LPTIM3_IN1, 

EVENTOUT

-

-

-

-

57

M12

79

K11

-

-

57

M12

79

K11

PD10

I/O FT_ha

-

LPTIM2_CH2, USART3_CK, 

TSC_G6_IO1, 

FMC_D15/FMC_AD15, 

SAI2_SCK_A, LPTIM3_ETR, 

EVENTOUT

-

-

-

-

58

J11

80

M13

-

-

58

J11

80

M13

PD11

I/O FT_ha

-

I2C4_SMBA, USART3_CTS, 

TSC_G6_IO2, 

FMC_CLE/FMC_A16, 

SAI2_SD_A, LPTIM2_ETR, 

EVENTOUT

ADC4_IN15

-

-

-

59

J12

81

K10

-

-

59

J12

81

K10

PD12

I/O

FT_

fha

-

TIM4_CH1, I2C4_SCL, 

USART3_RTS/USART3_DE, 

TSC_G6_IO3, 

FMC_ALE/FMC_A17, 

SAI2_FS_A, LPTIM2_IN1, 

EVENTOUT

ADC4_IN16

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

117/346

-

-

-

60

H11

82

K12

-

-

60

H11

82

K12

PD13

I/O

FT_

fha

-

TIM4_CH2, I2C4_SDA, 

TSC_G6_IO4, LPGPIO1_P6, 

FMC_A18, LPTIM4_IN1, 

LPTIM2_CH1, EVENTOUT

ADC4_IN17

-

-

-

-

-

83

J12

-

-

-

-

83

J12

VSS

S

-

-

-

-

-

-

-

-

-

84

J13

-

-

-

-

84

J13

VDD

S

-

-

-

-

-

-

G1

61

H10

85

J10

-

-

61

H10

85

J10

PD14

I/O

FT_h

-

TIM4_CH3, FMC_D0/FMC_AD0, 

LPTIM3_CH1, EVENTOUT

-

-

-

G3

62

H12

86

J11

-

-

62

H12

86

J11

PD15

I/O

FT_h

-

TIM4_CH4, FMC_D1/FMC_AD1, 

LPTIM3_CH2, EVENTOUT

-

-

-

-

-

G10

87

K13

-

-

-

G10

87

K13

PG2

I/O FT_hs

-

SPI1_SCK, FMC_A12, 

SAI2_SCK_B, EVENTOUT

-

-

-

-

-

G11

88

J8

-

-

-

G11

88

J8

PG3

I/O FT_hs

-

SPI1_MISO, FMC_A13, 

SAI2_FS_B, EVENTOUT

-

-

-

-

-

G9

89

H11

-

-

-

G9

89

H11

PG4

I/O FT_hs

-

SPI1_MOSI, FMC_A14, 

SAI2_MCLK_B, EVENTOUT

-

-

-

-

-

G12

90

J9

-

-

-

G12

90

J9

PG5

I/O FT_hs

-

SPI1_NSS, LPUART1_CTS, 

FMC_A15, SAI2_SD_B, 

EVENTOUT

-

-

-

-

-

F9

91

H10

-

-

-

F9

91

H10

PG6

I/O FT_hs

-

OCTOSPIM_P1_DQS, 

I2C3_SMBA, SPI1_RDY, 

LPUART1_RTS/LPUART1_DE, 

UCPD1_FRSTX1, EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

11

8/346

DS137

37 Rev 10

-

-

-

-

F10

92

G8

-

-

-

F10

92

G8

PG7

I/O FT_fhs

-

SAI1_CK1, I2C3_SCL, 
OCTOSPIM_P2_DQS, 

MDF1_CCK0, LPUART1_TX, 

UCPD1_FRSTX2, FMC_INT, 

SAI1_MCLK_A, EVENTOUT

-

-

-

-

-

F12

93

H9

-

-

-

F12

93

H9

PG8

I/O FT_fs

-

I2C3_SDA, LPUART1_RX, 

EVENTOUT

-

-

-

-

-

-

94

-

-

-

-

-

94

-

VSS

S

-

-

-

-

-

-

-

-

-

95

H12

-

-

-

-

95

H12

VDDIO2

S

-

-

-

-

-

37

G7

63

F11

96

H13

-

37

63

F11

96

H13

PC6

I/O

FT_a

-

CSLEEP, TIM3_CH1, TIM8_CH1, 

MDF1_CKI3, SDMMC1_D0DIR, 

TSC_G4_IO1, 

DCMI_D0/PSSI_D0, 

SDMMC2_D6, SDMMC1_D6, 

SAI2_MCLK_A, EVENTOUT

-

-

38

F4

64

E10

97

G12

-

38

64

E10

97

G12

PC7

I/O

FT_a

-

CDSTOP, TIM3_CH2, TIM8_CH2, 

MDF1_SDI3, 

SDMMC1_D123DIR, 

TSC_G4_IO2, 

DCMI_D1/PSSI_D1, 

SDMMC2_D7, SDMMC1_D7, 

SAI2_MCLK_B, LPTIM2_CH2, 

EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

119/346

-

39

F2

65

E12

98

G10

-

39

65

E12

98

G10

PC8

I/O

FT_a

-

SRDSTOP, TIM3_CH3, 

TIM8_CH3, TSC_G4_IO3, 

DCMI_D2/PSSI_D2, 

SDMMC1_D0, LPTIM3_CH1, 

EVENTOUT

-

-

40

F6

66

E11

99

G9

-

40

66

E11

99

G9

PC9

I/O

FT_a

-

TRACED0, TIM8_BKIN2, 

TIM3_CH4, TIM8_CH4, 

DCMI_D3/PSSI_D3, 

TSC_G4_IO4, OTG_FS_NOE, 

SDMMC1_D1, LPTIM3_CH2, 

EVENTOUT

-

29

41

F8

67

D12 100

G7

29

41

67

D12 100

G7

PA8

I/O FT_hv

-

MCO, TIM1_CH1, SAI1_CK2, 

SPI1_RDY, USART1_CK, 

OTG_FS_SOF, TRACECLK, 

SAI1_SCK_A, LPTIM2_CH1, 

EVENTOUT

-

30

42

E11

68

D10 101 G11

30

42

68

D10 101 G11

PA9

I/O

FT_u

-

TIM1_CH2, SPI2_SCK, 

DCMI_D0/PSSI_D0, 

USART1_TX(boot), SAI1_FS_A, 

TIM15_BKIN, EVENTOUT

OTG_FS_

VBUS

31

43

E1

69

D11 102 F11

31

43

69

D11 102 F11

PA10

I/O

FT_u

-

CRS_SYNC, TIM1_CH3, 

LPTIM2_IN2, SAI1_D1, 

DCMI_D1/PSSI_D1, 

USART1_RX(boot), OTG_FS_ID, 

SAI1_SD_A, TIM17_BKIN, 

EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

20/346

DS137

37 Rev 10

32

44

E3

70

C12 103 G13

32

44

70

C12 103 G13

PA11

I/O

FT_u

-

TIM1_CH4, TIM1_BKIN2, 

SPI1_MISO, USART1_CTS, 

FDCAN1_RX, EVENTOUT

OTG_FS_

DM(boot)

33

45

D2

71

B12 104 F13

33

45

71

B12 104 F13

PA12

I/O

FT_u

-

TIM1_ETR, SPI1_MOSI, 

OCTOSPIM_P2_NCS, 

USART1_RTS/USART1_DE, 

FDCAN1_TX, EVENTOUT

OTG_FS_

DP(boot)

34

46

D4

72

C10 105 F12

34

46

72

C10 105 F12

PA13 (JTMS/

SWDIO)

I/O

FT

(5)

JTMS/SWDIO, IR_OUT, 

OTG_FS_NOE, SAI1_SD_B, 

EVENTOUT

-

-

47

-

-

-

-

-

-

47

-

-

-

-

VSS

S

-

-

-

-

-

48

C1

73

A12 106 E13

-

48

73

A12 106 E13

VDDUSB

S

-

-

-

-

35

-

B2

74

H4

107 E12

35

-

74

H4

107 E12

VSS

S

-

-

-

-

36

-

A1

75

D9

108 D13

36

-

75

D9

108 D13

VDD

S

-

-

-

-

37

49

C3

76

C11 109 C10

37

49

76

C11 109 C10

PA14 (JTCK/

SWCLK)

I/O

FT

(5)

JTCK/SWCLK, LPTIM1_CH1, 

I2C1_SMBA, I2C4_SMBA, 

OTG_FS_SOF, SAI1_FS_B, 

EVENTOUT

-

38

50

E5

77

A11 110 A10

38

50

77

A11 110 A10

PA15 (JTDI)

I/O

FT_c

(4)
(5)

JTDI, TIM2_CH1, TIM2_ETR, 

USART2_RX, SPI1_NSS, 

SPI3_NSS, 

USART3_RTS/USART3_DE, 

UART4_RTS/UART4_DE, 

SAI2_FS_B, EVENTOUT

UCPD1_

CC1

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

1

21/346

-

51

E7

78

B11 111

C9

-

51

78

B11 111

C9

PC10

I/O

FT_a

-

TRACED1, LPTIM3_ETR, 

ADF1_CCK1, SPI3_SCK, 

USART3_TX(boot), UART4_TX, 

TSC_G3_IO2, 

DCMI_D8/PSSI_D8, 

LPGPIO1_P8, SDMMC1_D2, 

SAI2_SCK_B, EVENTOUT

-

-

52

A3

79

A10 112

A9

-

52

79

A10 112

A9

PC11

I/O FT_ha

-

LPTIM3_IN1, ADF1_SDI0, 

DCMI_D2/PSSI_D2, 

OCTOSPIM_P1_NCS, 

SPI3_MISO, USART3_RX(boot), 

UART4_RX, TSC_G3_IO3, 

DCMI_D4/PSSI_D4, 

UCPD1_FRSTX2, SDMMC1_D3, 

SAI2_MCLK_B, EVENTOUT

-

-

53

B4

80

B10 113

E8

-

53

80

B10 113

E8

PC12

I/O

FT_

hav

-

TRACED3, SPI3_MOSI, 

USART3_CK, UART5_TX, 

TSC_G3_IO4, 

DCMI_D9/PSSI_D9, 

LPGPIO1_P10, SDMMC1_CK, 

SAI2_SD_B, EVENTOUT

-

-

-

C5

81

C9

114

B9

-

-

81

C9

114

B9

PD0

I/O

FT_h

-

TIM8_CH4N, SPI2_NSS, 

FDCAN1_RX, 

FMC_D2/FMC_AD2, EVENTOUT

-

-

-

D6

82

B9

115

F6

-

-

82

B9

115

F6

PD1

I/O

FT_h

-

SPI2_SCK, FDCAN1_TX, 

FMC_D3/FMC_AD3, EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

22/346

DS137

37 Rev 10

-

54

A5

83

A9

116

F7

-

54

83

A9

116

F7

PD2

I/O

FT

-

TRACED2, TIM3_ETR, 

USART3_RTS/USART3_DE, 

UART5_RX, TSC_SYNC, 

DCMI_D11/PSSI_D11, 

LPGPIO1_P7, SDMMC1_CMD, 

LPTIM4_ETR, EVENTOUT

-

-

-

-

84

C8

117

D8

-

-

84

C8

117

D8

PD3

I/O FT_hv

-

SPI2_SCK, DCMI_D5/PSSI_D5, 

SPI2_MISO, MDF1_SDI0, 

USART2_CTS, 

OCTOSPIM_P2_NCS, 

FMC_CLK, EVENTOUT

-

-

-

D8

85

B8

118

C8

-

-

85

B8

118

C8

PD4

I/O

FT_h

-

SPI2_MOSI, MDF1_CKI0, 

USART2_RTS/USART2_DE, 

OCTOSPIM_P1_IO4, FMC_NOE, 

EVENTOUT

-

-

-

B6

86

A8

119

E7

-

-

86

A8

119

E7

PD5

I/O

FT_h

-

SPI2_RDY, USART2_TX, 

OCTOSPIM_P1_IO5, FMC_NWE, 

EVENTOUT

-

-

-

-

-

-

120

B8

-

-

-

-

120

B8

VSS

S

-

-

-

-

-

-

-

-

-

121

A8

-

-

-

-

121

A8

VDD

S

-

-

-

-

-

-

-

87

A7

122

B7

-

-

87

A7

122

B7

PD6

I/O FT_hv

-

SAI1_D1, DCMI_D10/PSSI_D10, 

SPI3_MOSI, MDF1_SDI1, 

USART2_RX, 

OCTOSPIM_P1_IO6, 

SDMMC2_CK, FMC_NWAIT, 

SAI1_SD_A, EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

1

23/346

-

-

-

88

D7

123

D7

-

-

88

D7

123

D7

PD7

I/O

FT_h

-

MDF1_CKI1, USART2_CK, 

OCTOSPIM_P1_IO7, 

SDMMC2_CMD, 

FMC_NCE/FMC_NE1, 

LPTIM4_OUT, EVENTOUT

-

-

-

C7

-

B7

124

A7

-

-

-

B7

124

A7

PG9

I/O FT_hs

-

OCTOSPIM_P2_IO6, 

SPI3_SCK(boot), USART1_TX, 

FMC_NCE/FMC_NE2, 

SAI2_SCK_A, TIM15_CH1N, 

EVENTOUT

-

-

-

A7

-

C7

125

C7

-

-

-

C7

125

C7

PG10

I/O FT_hs

-

LPTIM1_IN1, 

OCTOSPIM_P2_IO7, 

SPI3_MISO(boot), USART1_RX, 

FMC_NE3, SAI2_FS_A, 

TIM15_CH1, EVENTOUT

-

-

-

E9

-

-

-

-

-

-

-

M11 126 M10

PG11

I/O FT_hs

-

LPTIM1_IN2, 

OCTOSPIM_P1_IO5, 

SPI3_MOSI, USART1_CTS, 

SAI2_MCLK_A, TIM15_CH2, 

EVENTOUT

-

-

-

B8

-

A6

126

E6

-

-

-

A6

127

E6

PG12

I/O FT_hs

-

LPTIM1_ETR, 

OCTOSPIM_P2_NCS, 

SPI3_NSS(boot), 

USART1_RTS/USART1_DE, 

FMC_NE4, SAI2_SD_A, 

EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

24/346

DS137

37 Rev 10

-

-

C9

-

-

127

-

-

-

-

M10 128 N10

PG13

I/O FT_fhs

-

I2C1_SDA, SPI3_RDY, 

USART1_CK, FMC_A24, 

EVENTOUT

-

-

-

A9

-

-

128

-

-

-

-

M9

129

N9

PG14

I/O FT_fhs

-

LPTIM1_CH2, I2C1_SCL, 

FMC_A25, EVENTOUT

-

-

-

B10

-

H9

129

-

-

-

-

H9

130

-

VSS

S

-

-

-

-

-

-

A11

-

D8

130

A6

-

-

-

D8

131

A6

VDDIO2

S

-

-

-

-

-

-

-

-

-

131

A5

-

-

-

B4

132

A5

PG15

I/O FT_hs

-

LPTIM1_CH1, I2C1_SMBA, 

OCTOSPIM_P2_DQS, 

DCMI_D13/PSSI_D13, 

EVENTOUT

-

39

55

D10

89

C6

132

D6

39

55

89

C6

133

D6

PB3 

(JTDO/TRACES

WO)

I/O FT_fa

-

JTDO/TRACESWO, TIM2_CH2, 

LPTIM1_CH1, ADF1_CCK0, 

I2C1_SDA, SPI1_SCK, 

SPI3_SCK, 

USART1_RTS/USART1_DE, 

CRS_SYNC, LPGPIO1_P11, 

SDMMC2_D2, SAI1_SCK_B, 

EVENTOUT

COMP2_

INM2

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

1

25/346

40

56

C11

90

B6

133

B6

40

56

90

B6

134

B6

PB4 (NJTRST)

I/O FT_fa

(5)

NJTRST, LPTIM1_CH2, 

TIM3_CH1, ADF1_SDI0, 

I2C3_SDA, SPI1_MISO, 

SPI3_MISO, USART1_CTS, 

UART5_RTS/UART5_DE, 

TSC_G2_IO1, 

DCMI_D12/PSSI_D12, 

LPGPIO1_P12, SDMMC2_D3, 

SAI1_MCLK_B, TIM17_BKIN, 

EVENTOUT

COMP2_

INP1

41

57

D12

91

D6

134

C6

41

57

91

D6

135

C6

PB5

I/O

FT_

havd

-

LPTIM1_IN1, TIM3_CH2, 

OCTOSPIM_P1_NCLK, 

I2C1_SMBA, SPI1_MOSI, 

SPI3_MOSI(boot), USART1_CK, 

UART5_CTS, TSC_G2_IO2, 

DCMI_D10/PSSI_D10, 

COMP2_OUT, SAI1_SD_B, 

TIM16_BKIN, EVENTOUT

UCPD1_

DBCC1, 

WKUP6

42

58

A13

92

A5

135

B5

42

58

92

A5

136

B5

PB6

I/O FT_fa

-

LPTIM1_ETR, TIM4_CH1, 

TIM8_BKIN2, I2C1_SCL(boot), 

I2C4_SCL, MDF1_SDI5, 

USART1_TX, TSC_G2_IO3, 

DCMI_D5/PSSI_D5, SAI1_FS_B, 

TIM16_CH1N, EVENTOUT

COMP2_

INP2, 

WKUP3

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

26/346

DS137

37 Rev 10

43

59

B12

93

D5

136

F5

43

59

93

D5

137

F5

PB7

I/O

FT_

fhav

-

LPTIM1_IN2, TIM4_CH2, 

TIM8_BKIN, I2C1_SDA(boot), 

I2C4_SDA, MDF1_CKI5, 

USART1_RX, UART4_CTS, 

TSC_G2_IO4, 

DCMI_VSYNC/PSSI_RDY, 

FMC_NL, TIM17_CH1N, 

EVENTOUT

COMP2_

INM1, 

PVD_IN, 

WKUP4

44

60

C13

94

B5

137

C5

44

60

94

B5

138

C5

PH3-BOOT0

I/O

FT

-

EVENTOUT

-

45

61

B14

95

C5

138

E5

45

61

95

C5

139

E5

PB8

I/O

FT_f

-

TIM4_CH3, SAI1_CK1, 

I2C1_SCL, MDF1_CCK0, 

SPI3_RDY, SDMMC1_CKIN, 

FDCAN1_RX(boot), 

DCMI_D6/PSSI_D6, 

SDMMC2_D4, SDMMC1_D4, 

SAI1_MCLK_A, TIM16_CH1, 

EVENTOUT

WKUP5

-

-

A15

96

A4

139

D5

46

62

96

A4

140

D5

PB9

I/O

FT_f

-

IR_OUT, TIM4_CH4, SAI1_D2, 

I2C1_SDA, SPI2_NSS, 

SDMMC1_CDIR, 

FDCAN1_TX(boot), 

DCMI_D7/PSSI_D7, 

SDMMC2_D5, SDMMC1_D5, 

SAI1_FS_A, TIM17_CH1, 

EVENTOUT

-

-

-

-

97

C4

140

D4

-

-

97

C4

141

D4

PE0

I/O

FT_h

-

TIM4_ETR, DCMI_D2/PSSI_D2, 

LPGPIO1_P13, FMC_NBL0, 

TIM16_CH1, EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

1

27/346

-

-

-

-

A3

141

C4

-

-

98

A3

142

C4

PE1

I/O

FT_h

-

DCMI_D3/PSSI_D3, FMC_NBL1, 

TIM17_CH1, EVENTOUT

-

-

-

-

-

-

-

-

-

-

-

-

-

A4

VCAP

S

-

-

-

-

46

62

A17

98

B4

142

A4

-

-

-

-

-

-

VDD11

S

-

-

-

-

47

63

B16

99

E4

143

B4

47

63

99

E4

143

B4

VSS

S

-

-

-

-

48

64

B18 100

J9

144

A3

48

64

100

J9

144

A3

VDD

S

-

-

-

-

-

-

-

-

-

-

B11

-

-

-

-

-

B11

VSS

S

-

-

-

-

-

-

-

-

-

-

F10

-

-

-

-

-

F10

PH2

I/O

FT_h

-

OCTOSPIM_P1_IO4, 

EVENTOUT

-

-

-

-

-

-

-

E10

-

-

-

-

-

E10

PH4

I/O FT_fh

-

I2C2_SCL, 

OCTOSPIM_P2_DQS, 

PSSI_D14, EVENTOUT

-

-

-

-

-

-

-

F9

-

-

-

-

-

F9

PH5

I/O

FT_f

-

I2C2_SDA, 

DCMI_PIXCLK/PSSI_PDCK, 

EVENTOUT

-

-

-

-

-

-

-

E11

-

-

-

-

-

E11

PH6

I/O FT_hv

-

I2C2_SMBA, 

OCTOSPIM_P2_CLK, 

DCMI_D8/PSSI_D8, EVENTOUT

-

-

-

-

-

-

-

F8

-

-

-

-

-

F8

PH7

I/O

FT_

fhv

-

I2C3_SCL, 

OCTOSPIM_P2_NCLK, 

DCMI_D9/PSSI_D9, EVENTOUT

-

-

-

-

-

-

-

D12

-

-

-

-

-

D12

PH8

I/O FT_fh

-

I2C3_SDA, OCTOSPIM_P2_IO3, 

DCMI_HSYNC/PSSI_DE, 

EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

28/346

DS137

37 Rev 10

-

-

-

-

-

-

E9

-

-

-

-

-

E9

PH9

I/O

FT_h

-

I2C3_SMBA, 

OCTOSPIM_P2_IO4, 

DCMI_D0/PSSI_D0, EVENTOUT

-

-

-

-

-

-

-

C13

-

-

-

-

-

C13

PH10

I/O

FT_h

-

TIM5_CH1, OCTOSPIM_P2_IO5, 

DCMI_D1/PSSI_D1, EVENTOUT

-

-

-

-

-

-

-

D9

-

-

-

-

-

D9

PH11

I/O

FT_h

-

TIM5_CH2, OCTOSPIM_P2_IO6, 

DCMI_D2/PSSI_D2, EVENTOUT

-

-

-

-

-

-

-

B13

-

-

-

-

-

B13

PH12

I/O

FT_h

-

TIM5_CH3, TIM8_CH4N, 

OCTOSPIM_P2_IO7, 

DCMI_D3/PSSI_D3, EVENTOUT

-

-

-

-

-

-

-

C12

-

-

-

-

-

C12

PH13

I/O

FT

-

TIM8_CH1N, FDCAN1_TX, 

EVENTOUT

-

-

-

-

-

-

-

C11

-

-

-

-

-

C11

PH14

I/O

FT

-

TIM8_CH2N, FDCAN1_RX, 

DCMI_D4/PSSI_D4, EVENTOUT

-

-

-

-

-

-

-

A13

-

-

-

-

-

A13

PH15

I/O

FT_h

-

TIM8_CH3N, 

OCTOSPIM_P2_IO6, 

DCMI_D11/PSSI_D11, 

EVENTOUT

-

-

-

-

-

-

-

A11

-

-

-

-

-

A11

VDD

S

-

-

-

-

-

-

-

-

-

-

B12

-

-

-

-

-

B12

PI0

I/O

FT_h

-

TIM5_CH4, OCTOSPIM_P1_IO5, 

SPI2_NSS, 

DCMI_D13/PSSI_D13, 

EVENTOUT

-

-

-

-

-

-

-

A12

-

-

-

-

-

A12

PI1

I/O

FT_h

-

SPI2_SCK, OCTOSPIM_P2_IO2, 

DCMI_D8/PSSI_D8, EVENTOUT

-

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

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-

-

-

-

-

-

D11

-

-

-

-

-

D11

PI2

I/O FT_hv

-

TIM8_CH4, SPI2_MISO, 

OCTOSPIM_P2_IO1, 

DCMI_D9/PSSI_D9, EVENTOUT

-

-

-

-

-

-

-

D10

-

-

-

-

-

D10

PI3

I/O

FT_h

-

TIM8_ETR, SPI2_MOSI, 

OCTOSPIM_P2_IO0, 

DCMI_D10/PSSI_D10, 

EVENTOUT

-

-

-

-

-

-

-

B2

-

-

-

-

-

B2

VSS

S

-

-

-

-

-

-

-

-

-

-

B1

-

-

-

-

-

B1

VDD

S

-

-

-

-

-

-

-

-

-

-

B10

-

-

-

-

-

B10

PI4

I/O

FT

-

TIM8_BKIN, SPI2_RDY, 

DCMI_D5/PSSI_D5, EVENTOUT

-

-

-

-

-

-

-

B3

-

-

-

-

-

B3

PI5

I/O

FT_h

-

TIM8_CH1, 

OCTOSPIM_P2_NCS, 

DCMI_VSYNC/PSSI_RDY, 

EVENTOUT

-

-

-

-

-

-

-

A2

-

-

-

-

-

A2

PI6

I/O FT_hv

-

TIM8_CH2, 

OCTOSPIM_P2_CLK, 

DCMI_D6/PSSI_D6, EVENTOUT

-

-

-

-

-

-

-

C3

-

-

-

-

-

C3

PI7

I/O FT_hv

-

TIM8_CH3, 

OCTOSPIM_P2_NCLK, 

DCMI_D7/PSSI_D7, EVENTOUT

-

1. Function availability depends on the chosen device.

2. PC13, PC14 and PC15 are supplied through the power switch (by V

SW

). Since the switch only sinks a limited amount of current (3 mA), the use of PC13 to PC15 GPIOs 

in output mode is limited: 

- PC13 speed must not exceed 2 MHz with a maximum load of 30 pF. Refer to FT_o electrical characteristics for PC14, PC15.
- These GPIOs must not be used as current sources (for example to drive a LED).

Table 26. STM32U575xx pin definitions

(1)

 (continued)

Pin number

Pin name 

(function after 

reset)

Pi

n t

y

pe

I/O

 s

tru

ct

ure

Notes

Alternate functions

Additional 

functions

LQ

FP

48 SMP

S

U

F

QF

PN

48 S

M

PS

LQ

FP

64 SMP

S

W

L

C

S

P

90 SMPS

LQFP100 SMPS

UFBGA132 SMPS

LQFP144 SMPS

UFBGA169 SMPS

LQFP

48

UFQFPN48

LQFP

64

LQF

P

10

0

UFBGA

132

LQF

P

14

4

UFBGA

169

STM32U575RGT6-html.html

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ST
M32

U

57

5x

x

1

30/346

DS137

37 Rev 10

3. After a backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the 

system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual. 

4. After reset, a pull-down resistor (Rd = 5.1 k

 from UCPD peripheral) can be activated on PA15 and PB15 (UCPD1_CC1, UCPD1_CC2). The pull-down on PA15 

(UCPD1_CC1) is activated by high level on PB5 (UCPD1_DBCC1). The pull-down on PB15 (UCPD1_CC2) is activated by high level on PB14 (UCPD1_DBCC2). 

This pull-down control (dead battery support on UCPD) can be disabled by setting UCPD_DBDIS = 1 in the PWR_UCPDR register. 

5. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

STM32U575RGT6-html.html

STM32

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575
xx

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4.3 Alternate 

functions

          

STM32U575RGT6-html.html

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ST
M32

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x

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DS137

37 Rev 10

Table 27. Alternate function AF0 to AF7

(1)

 

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

CRS/LPTIM1/

SYS_AF

LPTIM1/

TIM1/2/5/8

LPTIM1/2/3/

TIM1/2/3/4/5

ADF1/I2C4/

OCTOSPIM_P1/

OTG_FS/SAI1/

SPI2/TIM1/8/

USART2

DCMI/

I2C1/2/3/4/

LPTIM3

DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/

SPI1/2/3

I2C3/MDF1/

OCTOSPIM_P2/

SPI3

USART1/2/3

Port A

PA0

-

TIM2_CH1

TIM5_CH1

TIM8_ETR

-

-

SPI3_RDY

USART2_CTS

PA1

LPTIM1_CH2

TIM2_CH2

TIM5_CH2

-

I2C1_SMBA

SPI1_SCK

-

USART2_

RTS/USART2_

DE

PA2

-

TIM2_CH3

TIM5_CH3

-

-

SPI1_RDY

-

USART2_TX

PA3

-

TIM2_CH4

TIM5_CH4

SAI1_CK1

-

-

-

USART2_RX

PA4

-

-

-

OCTOSPIM_P1

_NCS

-

SPI1_NSS

SPI3_NSS

USART2_CK

PA5

CSLEEP

TIM2_CH1

TIM2_ETR

TIM8_CH1N

PSSI_D14

SPI1_SCK

-

USART3_RX

PA6

CDSTOP

TIM1_BKIN

TIM3_CH1

TIM8_BKIN

DCMI_PIXCL

K/PSSI_

PDCK

SPI1_MISO

-

USART3_CTS

PA7

SRDSTOP

TIM1_CH1N

TIM3_CH2

TIM8_CH1N

I2C3_SCL

SPI1_MOSI

-

USART3_TX

PA8

MCO

TIM1_CH1

-

SAI1_CK2

-

SPI1_RDY

-

USART1_CK

PA9

-

TIM1_CH2

-

SPI2_SCK

-

DCMI_D0/PSSI_D0

-

USART1_TX

PA10

CRS_SYNC

TIM1_CH3

LPTIM2_IN2

SAI1_D1

-

DCMI_D1/PSSI_D1

-

USART1_RX

PA11

-

TIM1_CH4

TIM1_BKIN2

-

-

SPI1_MISO

-

USART1_CTS

PA12

-

TIM1_ETR

-

-

-

SPI1_MOSI

OCTOSPIM_

P2_NCS

USART1_

RTS/USART1_

DE

PA13

JTMS/SWDIO

IR_OUT

-

-

-

-

-

-

PA14

JTCK/SWCLK

LPTIM1_CH1

-

-

I2C1_SMBA

I2C4_SMBA

-

-

PA15

JTDI

TIM2_CH1

TIM2_ETR

USART2_RX

-

SPI1_NSS

SPI3_NSS

USART3_

RTS/USART3_

DE

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

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Port B

PB0

-

TIM1_CH2N

TIM3_CH3

TIM8_CH2N

LPTIM3_CH1

SPI1_NSS

-

USART3_CK

PB1

-

TIM1_CH3N

TIM3_CH4

TIM8_CH3N

LPTIM3_CH2

-

MDF1_SDI0

USART3_

RTS/USART3_

DE

PB2

-

LPTIM1_CH1

-

TIM8_CH4N

I2C3_SMBA

SPI1_RDY

MDF1_CKI0

-

PB3

JTDO/

TRACESWO

TIM2_CH2

LPTIM1_CH1

ADF1_CCK0

I2C1_SDA

SPI1_SCK

SPI3_SCK

USART1_

RTS/USART1_

DE

PB4

NJTRST

LPTIM1_CH2

TIM3_CH1

ADF1_SDI0

I2C3_SDA

SPI1_MISO

SPI3_MISO

USART1_CTS

PB5

-

LPTIM1_IN1

TIM3_CH2

OCTOSPIM_

P1_NCLK

I2C1_SMBA

SPI1_MOSI

SPI3_MOSI

USART1_CK

PB6

-

LPTIM1_ETR

TIM4_CH1

TIM8_BKIN2

I2C1_SCL

I2C4_SCL

MDF1_SDI5

USART1_TX

PB7

-

LPTIM1_IN2

TIM4_CH2

TIM8_BKIN

I2C1_SDA

I2C4_SDA

MDF1_CKI5

USART1_RX

PB8

-

-

TIM4_CH3

SAI1_CK1

I2C1_SCL

MDF1_CCK0

SPI3_RDY

-

PB9

-

IR_OUT

TIM4_CH4

SAI1_D2

I2C1_SDA

SPI2_NSS

-

-

PB10

-

TIM2_CH3

LPTIM3_CH1

I2C4_SCL

I2C2_SCL

SPI2_SCK

-

USART3_TX

PB11

-

TIM2_CH4

-

I2C4_SDA

I2C2_SDA

SPI2_RDY

-

USART3_RX

PB12

-

TIM1_BKIN

-

-

I2C2_SMBA

SPI2_NSS

MDF1_SDI1

USART3_CK

PB13

-

TIM1_CH1N

LPTIM3_IN1

-

I2C2_SCL

SPI2_SCK

MDF1_CKI1

USART3_CTS

PB14

-

TIM1_CH2N

LPTIM3_ETR

TIM8_CH2N

I2C2_SDA

SPI2_MISO

MDF1_SDI2

USART3_

RTS/USART3_

DE

PB15

RTC_REFIN

TIM1_CH3N

LPTIM2_IN2

TIM8_CH3N

-

SPI2_MOSI

MDF1_CKI2

-

Table 27. Alternate function AF0 to AF7

(1)

 (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

CRS/LPTIM1/

SYS_AF

LPTIM1/

TIM1/2/5/8

LPTIM1/2/3/

TIM1/2/3/4/5

ADF1/I2C4/

OCTOSPIM_P1/

OTG_FS/SAI1/

SPI2/TIM1/8/

USART2

DCMI/

I2C1/2/3/4/

LPTIM3

DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/

SPI1/2/3

I2C3/MDF1/

OCTOSPIM_P2/

SPI3

USART1/2/3

STM32U575RGT6-html.html

Pin
out
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ript
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e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

34/346

DS137

37 Rev 10

Port C

PC0

-

LPTIM1_IN1

-

OCTOSPIM_

P1_IO7

I2C3_SCL

SPI2_RDY

MDF1_SDI4

-

PC1

TRACED0

LPTIM1_CH1

-

SPI2_MOSI

I2C3_SDA

-

MDF1_CKI4

-

PC2

-

LPTIM1_IN2

-

-

-

SPI2_MISO

MDF1_CCK1

-

PC3

-

LPTIM1_ETR

LPTIM3_CH1

SAI1_D1

-

SPI2_MOSI

-

-

PC4

-

-

-

-

-

-

-

USART3_TX

PC5

-

TIM1_CH4N

-

SAI1_D3

PSSI_D15

-

-

USART3_RX

PC6

CSLEEP

-

TIM3_CH1

TIM8_CH1

-

-

MDF1_CKI3

-

PC7

CDSTOP

-

TIM3_CH2

TIM8_CH2

-

-

MDF1_SDI3

-

PC8

SRDSTOP

-

TIM3_CH3

TIM8_CH3

-

-

-

-

PC9

TRACED0

TIM8_BKIN2

TIM3_CH4

TIM8_CH4

DCMI_D3/

PSSI_D3

-

-

-

PC10

TRACED1

-

LPTIM3_ETR

ADF1_CCK1

-

-

SPI3_SCK

USART3_TX

PC11

-

-

LPTIM3_IN1

ADF1_SDI0

DCMI_D2/

PSSI_D2

OCTOSPIM_

P1_NCS

SPI3_MISO

USART3_RX

PC12

TRACED3

-

-

-

-

-

SPI3_MOSI

USART3_CK

PC13

-

-

-

-

-

-

-

-

PC14

-

-

-

-

-

-

-

-

PC15

-

-

-

-

-

-

-

-

Table 27. Alternate function AF0 to AF7

(1)

 (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

CRS/LPTIM1/

SYS_AF

LPTIM1/

TIM1/2/5/8

LPTIM1/2/3/

TIM1/2/3/4/5

ADF1/I2C4/

OCTOSPIM_P1/

OTG_FS/SAI1/

SPI2/TIM1/8/

USART2

DCMI/

I2C1/2/3/4/

LPTIM3

DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/

SPI1/2/3

I2C3/MDF1/

OCTOSPIM_P2/

SPI3

USART1/2/3

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

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in de

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rip
tion an

d alter

n

at

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io

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DS137

37 Rev 10

1

35/346

Port D

PD0

-

-

-

TIM8_CH4N

-

SPI2_NSS

-

-

PD1

-

-

-

-

-

SPI2_SCK

-

-

PD2

TRACED2

-

TIM3_ETR

-

-

-

-

USART3_

RTS/USART3_

DE

PD3

-

-

-

SPI2_SCK

DCMI_D5/

PSSI_D5

SPI2_MISO

MDF1_SDI0

USART2_CTS

PD4

-

-

-

-

-

SPI2_MOSI

MDF1_CKI0

USART2_

RTS/USART2_

DE

PD5

-

-

-

-

-

SPI2_RDY

-

USART2_TX

PD6

-

-

-

SAI1_D1

DCMI_D10/

PSSI_D10

SPI3_MOSI

MDF1_SDI1

USART2_RX

PD7

-

-

-

-

-

-

MDF1_CKI1

USART2_CK

PD8

-

-

-

-

-

-

-

USART3_TX

PD9

-

-

LPTIM2_IN2

-

-

-

-

USART3_RX

PD10

-

-

LPTIM2_CH2

-

-

-

-

USART3_CK

PD11

-

-

-

-

I2C4_SMBA

-

-

USART3_CTS

PD12

-

-

TIM4_CH1

-

I2C4_SCL

-

-

USART3_

RTS/USART3_

DE

PD13

-

-

TIM4_CH2

-

I2C4_SDA

-

-

-

PD14

-

-

TIM4_CH3

-

-

-

-

-

PD15

-

-

TIM4_CH4

-

-

-

-

-

Table 27. Alternate function AF0 to AF7

(1)

 (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

CRS/LPTIM1/

SYS_AF

LPTIM1/

TIM1/2/5/8

LPTIM1/2/3/

TIM1/2/3/4/5

ADF1/I2C4/

OCTOSPIM_P1/

OTG_FS/SAI1/

SPI2/TIM1/8/

USART2

DCMI/

I2C1/2/3/4/

LPTIM3

DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/

SPI1/2/3

I2C3/MDF1/

OCTOSPIM_P2/

SPI3

USART1/2/3

STM32U575RGT6-html.html

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e

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te

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tions

ST
M32

U

57

5x

x

1

36/346

DS137

37 Rev 10

Port E

PE0

-

-

TIM4_ETR

-

-

-

-

-

PE1

-

-

-

-

-

-

-

-

PE2

TRACECLK

-

TIM3_ETR

SAI1_CK1

-

-

-

-

PE3

TRACED0

-

TIM3_CH1

OCTOSPIM_

P1_DQS

-

-

-

-

PE4

TRACED1

-

TIM3_CH2

SAI1_D2

-

-

MDF1_SDI3

-

PE5

TRACED2

-

TIM3_CH3

SAI1_CK2

-

-

MDF1_CKI3

-

PE6

TRACED3

-

TIM3_CH4

SAI1_D1

-

-

-

-

PE7

-

TIM1_ETR

-

-

-

-

MDF1_SDI2

-

PE8

-

TIM1_CH1N

-

-

-

-

MDF1_CKI2

-

PE9

-

TIM1_CH1

-

ADF1_CCK0

-

-

MDF1_CCK0

-

PE10

-

TIM1_CH2N

-

ADF1_SDI0

-

-

MDF1_SDI4

-

PE11

-

TIM1_CH2

-

-

-

SPI1_RDY

MDF1_CKI4

-

PE12

-

TIM1_CH3N

-

-

-

SPI1_NSS

MDF1_SDI5

-

PE13

-

TIM1_CH3

-

-

-

SPI1_SCK

MDF1_CKI5

-

PE14

-

TIM1_CH4

TIM1_BKIN2

-

-

SPI1_MISO

-

-

PE15

-

TIM1_BKIN

-

TIM1_CH4N

-

SPI1_MOSI

-

-

Table 27. Alternate function AF0 to AF7

(1)

 (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

CRS/LPTIM1/

SYS_AF

LPTIM1/

TIM1/2/5/8

LPTIM1/2/3/

TIM1/2/3/4/5

ADF1/I2C4/

OCTOSPIM_P1/

OTG_FS/SAI1/

SPI2/TIM1/8/

USART2

DCMI/

I2C1/2/3/4/

LPTIM3

DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/

SPI1/2/3

I2C3/MDF1/

OCTOSPIM_P2/

SPI3

USART1/2/3

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

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io

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s

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37 Rev 10

1

37/346

Port F

PF0

-

-

-

-

I2C2_SDA

OCTOSPIM_P2_IO0

-

-

PF1

-

-

-

-

I2C2_SCL

OCTOSPIM_P2_IO1

-

-

PF2

-

-

LPTIM3_CH2

-

I2C2_SMBA OCTOSPIM_P2_IO2

-

-

PF3

-

-

LPTIM3_IN1

-

-

OCTOSPIM_P2_IO3

-

-

PF4

-

-

LPTIM3_ETR

-

-

OCTOSPIM_

P2_CLK

-

-

PF5

-

-

LPTIM3_CH1

-

-

OCTOSPIM_

P2_NCLK

-

-

PF6

-

TIM5_ETR

TIM5_CH1

-

DCMI_D12/P

SSI_D12

OCTOSPIM_

P2_NCS

-

-

PF7

-

-

TIM5_CH2

-

-

-

-

-

PF8

-

-

TIM5_CH3

-

PSSI_D14

-

-

-

PF9

-

-

TIM5_CH4

-

PSSI_D15

-

-

-

PF10

-

-

-

OCTOSPIM_

P1_CLK

PSSI_D15

-

MDF1_CCK1

-

PF11

-

-

-

OCTOSPIM_

P1_NCLK

-

-

-

-

PF12

-

-

-

-

-

OCTOSPIM_

P2_DQS

-

-

PF13

-

-

-

-

I2C4_SMBA

-

-

-

PF14

-

-

-

-

I2C4_SCL

-

-

-

PF15

-

-

-

-

I2C4_SDA

-

-

-

Table 27. Alternate function AF0 to AF7

(1)

 (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

CRS/LPTIM1/

SYS_AF

LPTIM1/

TIM1/2/5/8

LPTIM1/2/3/

TIM1/2/3/4/5

ADF1/I2C4/

OCTOSPIM_P1/

OTG_FS/SAI1/

SPI2/TIM1/8/

USART2

DCMI/

I2C1/2/3/4/

LPTIM3

DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/

SPI1/2/3

I2C3/MDF1/

OCTOSPIM_P2/

SPI3

USART1/2/3

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

38/346

DS137

37 Rev 10

Port G

PG0

-

-

-

-

-

OCTOSPIM_P2_IO4

-

-

PG1

-

-

-

-

-

OCTOSPIM_P2_IO5

-

-

PG2

-

-

-

-

-

SPI1_SCK

-

-

PG3

-

-

-

-

-

SPI1_MISO

-

-

PG4

-

-

-

-

-

SPI1_MOSI

-

-

PG5

-

-

-

-

-

SPI1_NSS

-

-

PG6

-

-

-

OCTOSPIM_

P1_DQS

I2C3_SMBA

SPI1_RDY

-

-

PG7

-

-

-

SAI1_CK1

I2C3_SCL

OCTOSPIM_

P2_DQS

MDF1_CCK0

-

PG8

-

-

-

-

I2C3_SDA

-

-

-

PG9

-

-

-

-

-

OCTOSPIM_P2_IO6

SPI3_SCK

USART1_TX

PG10

-

LPTIM1_IN1

-

-

-

OCTOSPIM_P2_IO7

SPI3_MISO

USART1_RX

PG11

-

LPTIM1_IN2

-

OCTOSPIM_

P1_IO5

-

-

SPI3_MOSI

USART1_CTS

PG12

-

LPTIM1_ETR

-

-

-

OCTOSPIM_

P2_NCS

SPI3_NSS

USART1_

RTS/USART1_

DE

PG13

-

-

-

-

I2C1_SDA

-

SPI3_RDY

USART1_CK

PG14

-

LPTIM1_CH2

-

-

I2C1_SCL

-

-

-

PG15

-

LPTIM1_CH1

-

-

I2C1_SMBA

OCTOSPIM_

P2_DQS

-

-

Table 27. Alternate function AF0 to AF7

(1)

 (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

CRS/LPTIM1/

SYS_AF

LPTIM1/

TIM1/2/5/8

LPTIM1/2/3/

TIM1/2/3/4/5

ADF1/I2C4/

OCTOSPIM_P1/

OTG_FS/SAI1/

SPI2/TIM1/8/

USART2

DCMI/

I2C1/2/3/4/

LPTIM3

DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/

SPI1/2/3

I2C3/MDF1/

OCTOSPIM_P2/

SPI3

USART1/2/3

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

1

39/346

Port H

PH0

-

-

-

-

-

-

-

-

PH1

-

-

-

-

-

-

-

-

PH2

-

-

-

OCTOSPIM_

P1_IO4

-

-

-

-

PH3

-

-

-

-

-

-

-

-

PH4

-

-

-

-

I2C2_SCL

OCTOSPIM_

P2_DQS

-

-

PH5

-

-

-

-

I2C2_SDA

-

-

-

PH6

-

-

-

-

I2C2_SMBA

OCTOSPIM_

P2_CLK

-

-

PH7

-

-

-

-

I2C3_SCL

OCTOSPIM_

P2_NCLK

-

-

PH8

-

-

-

-

I2C3_SDA

OCTOSPIM_P2_IO3

-

-

PH9

-

-

-

-

I2C3_SMBA OCTOSPIM_P2_IO4

-

-

PH10

-

-

TIM5_CH1

-

-

OCTOSPIM_P2_IO5

-

-

PH11

-

-

TIM5_CH2

-

-

OCTOSPIM_P2_IO6

-

-

PH12

-

-

TIM5_CH3

TIM8_CH4N

-

OCTOSPIM_P2_IO7

-

-

PH13

-

-

-

TIM8_CH1N

-

-

-

-

PH14

-

-

-

TIM8_CH2N

-

-

-

-

PH15

-

-

-

TIM8_CH3N

-

OCTOSPIM_P2_IO6

-

-

Table 27. Alternate function AF0 to AF7

(1)

 (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

CRS/LPTIM1/

SYS_AF

LPTIM1/

TIM1/2/5/8

LPTIM1/2/3/

TIM1/2/3/4/5

ADF1/I2C4/

OCTOSPIM_P1/

OTG_FS/SAI1/

SPI2/TIM1/8/

USART2

DCMI/

I2C1/2/3/4/

LPTIM3

DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/

SPI1/2/3

I2C3/MDF1/

OCTOSPIM_P2/

SPI3

USART1/2/3

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

40/346

DS137

37 Rev 10

Port I

PI0

-

-

TIM5_CH4

OCTOSPIM_

P1_IO5

-

SPI2_NSS

-

-

PI1

-

-

-

-

-

SPI2_SCK

OCTOSPIM_

P2_IO2

-

PI2

-

-

-

TIM8_CH4

-

SPI2_MISO

OCTOSPIM_

P2_IO1

-

PI3

-

-

-

TIM8_ETR

-

SPI2_MOSI

OCTOSPIM_

P2_IO0

-

PI4

-

-

-

TIM8_BKIN

-

SPI2_RDY

-

-

PI5

-

-

-

TIM8_CH1

-

OCTOSPIM_

P2_NCS

-

-

PI6

-

-

-

TIM8_CH2

-

OCTOSPIM_

P2_CLK

-

-

PI7

-

-

-

TIM8_CH3

-

OCTOSPIM_

P2_NCLK

-

-

1. Refer to the next table for AF8 to AF15.

Table 27. Alternate function AF0 to AF7

(1)

 (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

CRS/LPTIM1/

SYS_AF

LPTIM1/

TIM1/2/5/8

LPTIM1/2/3/

TIM1/2/3/4/5

ADF1/I2C4/

OCTOSPIM_P1/

OTG_FS/SAI1/

SPI2/TIM1/8/

USART2

DCMI/

I2C1/2/3/4/

LPTIM3

DCMI/I2C4/MDF1/
OCTOSPIM_P1/2/

SPI1/2/3

I2C3/MDF1/

OCTOSPIM_P2/

SPI3

USART1/2/3

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

1

41/346

          

Table 28. Alternate function AF8 to AF15

(1)

 

Port

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

LPUART1/

SDMMC1/

UART4/5

CAN1/TSC

CRS/DCMI/

OCTOSPIM_P1/2/

OTG_FS

LPGPIO1/
SDMMC2/

UCPD1/FMC

COMP1/2/FMC/

SDMMC1/2

LPTIM2/4/

SAI1/2

LPTIM2/3/

TIM2/15/16/17

EVENTOUT

Port A

PA0

UART4_TX

-

OCTOSPIM_

P2_NCS

-

SDMMC2_CMD

AUDIOCLK

TIM2_ETR

EVENTOUT

PA1

UART4_RX

-

OCTOSPIM_

P1_DQS

LPGPIO1_P0

-

-

TIM15_CH1N

EVENTOUT

PA2

LPUART1_TX

-

OCTOSPIM_

P1_NCS

UCPD1_

FRSTX1

-

-

TIM15_CH1

EVENTOUT

PA3

LPUART1_RX

-

OCTOSPIM_P1_CLK

LPGPIO1_P1

-

SAI1_MCLK_A

TIM15_CH2

EVENTOUT

PA4

-

-

DCMI_HSYNC/

PSSI_DE

-

-

SAI1_FS_B

LPTIM2_CH1

EVENTOUT

PA5

-

-

-

-

-

-

LPTIM2_ETR

EVENTOUT

PA6

LPUART1_CTS

-

OCTOSPIM_P1_IO3

LPGPIO1_P2

-

-

TIM16_CH1

EVENTOUT

PA7

-

-

OCTOSPIM_P1_IO2

-

-

LPTIM2_CH2

TIM17_CH1

EVENTOUT

PA8

-

-

OTG_FS_SOF

-

TRACECLK

SAI1_SCK_A

LPTIM2_CH1

EVENTOUT

PA9

-

-

-

-

-

SAI1_FS_A

TIM15_BKIN

EVENTOUT

PA10

-

-

OTG_FS_ID

-

-

SAI1_SD_A

TIM17_BKIN

EVENTOUT

PA11

-

FDCAN1_RX

-

-

-

-

-

EVENTOUT

PA12

-

FDCAN1_TX

-

-

-

-

-

EVENTOUT

PA13

-

-

OTG_FS_NOE

-

-

SAI1_SD_B

-

EVENTOUT

PA14

-

-

OTG_FS_SOF

-

-

SAI1_FS_B

-

EVENTOUT

PA15

UART4_RTS/

UART4_DE

-

-

-

-

SAI2_FS_B

-

EVENTOUT

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

42/346

DS137

37 Rev 10

Port B

PB0

-

-

OCTOSPIM_P1_IO1

LPGPIO1_P9

COMP1_OUT

AUDIOCLK

-

EVENTOUT

PB1

LPUART1_

RTS/LPUART1_

DE

-

OCTOSPIM_P1_IO0

LPGPIO1_P3

-

-

LPTIM2_IN1

EVENTOUT

PB2

-

-

OCTOSPIM_

P1_DQS

UCPD1_

FRSTX1

-

-

-

EVENTOUT

PB3

-

-

CRS_SYNC

LPGPIO1_P11

SDMMC2_D2

SAI1_SCK_B

-

EVENTOUT

PB4

UART5_RTS/

UART5_DE

TSC_G2_IO1

DCMI_D12/

PSSI_D12

LPGPIO1_P12

SDMMC2_D3

SAI1_MCLK_B

TIM17_BKIN

EVENTOUT

PB5

UART5_CTS

TSC_G2_IO2

DCMI_D10/

PSSI_D10

-

COMP2_OUT

SAI1_SD_B

TIM16_BKIN

EVENTOUT

PB6

-

TSC_G2_IO3

DCMI_D5/PSSI_D5

-

-

SAI1_FS_B

TIM16_CH1N

EVENTOUT

PB7

UART4_CTS

TSC_G2_IO4

DCMI_VSYNC/

PSSI_RDY

-

FMC_NL

-

TIM17_CH1N

EVENTOUT

PB8

SDMMC1_CKIN

FDCAN1_RX

DCMI_D6/PSSI_D6

SDMMC2_D4

SDMMC1_D4

SAI1_MCLK_A

TIM16_CH1

EVENTOUT

PB9

SDMMC1_CDIR

FDCAN1_TX

DCMI_D7/PSSI_D7

SDMMC2_D5

SDMMC1_D5

SAI1_FS_A

TIM17_CH1

EVENTOUT

PB10

LPUART1_RX

TSC_SYNC

OCTOSPIM_P1_CLK

LPGPIO1_P4

COMP1_OUT

SAI1_SCK_A

-

EVENTOUT

PB11

LPUART1_TX

-

OCTOSPIM_

P1_NCS

-

COMP2_OUT

-

-

EVENTOUT

PB12

LPUART1_RTS/

LPUART1_DE

TSC_G1_IO1

OCTOSPIM_

P1_NCLK

-

-

SAI2_FS_A

TIM15_BKIN

EVENTOUT

PB13

LPUART1_CTS

TSC_G1_IO2

-

-

-

SAI2_SCK_A

TIM15_CH1N

EVENTOUT

PB14

-

TSC_G1_IO3

-

-

SDMMC2_D0

SAI2_MCLK_A

TIM15_CH1

EVENTOUT

PB15

-

-

-

FMC_NBL1

SDMMC2_D1

SAI2_SD_A

TIM15_CH2

EVENTOUT

Table 28. Alternate function AF8 to AF15

(1)

 (continued)

Port

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

LPUART1/

SDMMC1/

UART4/5

CAN1/TSC

CRS/DCMI/

OCTOSPIM_P1/2/

OTG_FS

LPGPIO1/
SDMMC2/

UCPD1/FMC

COMP1/2/FMC/

SDMMC1/2

LPTIM2/4/

SAI1/2

LPTIM2/3/

TIM2/15/16/17

EVENTOUT

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

1

43/346

Port C

PC0

LPUART1_RX

-

-

-

SDMMC1_D5

SAI2_FS_A

LPTIM2_IN1

EVENTOUT

PC1

LPUART1_TX

-

OCTOSPIM_P1_IO4

-

SDMMC2_CK

SAI1_SD_A

-

EVENTOUT

PC2

-

-

OCTOSPIM_P1_IO5

LPGPIO1_P5

-

-

-

EVENTOUT

PC3

-

-

OCTOSPIM_P1_IO6

-

-

SAI1_SD_A

LPTIM2_ETR

EVENTOUT

PC4

-

-

OCTOSPIM_P1_IO7

-

-

-

-

EVENTOUT

PC5

-

-

-

-

-

-

-

EVENTOUT

PC6

SDMMC1_

D0DIR

TSC_G4_IO1

DCMI_D0/PSSI_D0

SDMMC2_D6

SDMMC1_D6

SAI2_MCLK_A

-

EVENTOUT

PC7

SDMMC1_

D123DIR

TSC_G4_IO2

DCMI_D1/PSSI_D1

SDMMC2_D7

SDMMC1_D7

SAI2_MCLK_B

LPTIM2_CH2

EVENTOUT

PC8

-

TSC_G4_IO3

DCMI_D2/PSSI_D2

-

SDMMC1_D0

-

LPTIM3_CH1

EVENTOUT

PC9

-

TSC_G4_IO4

OTG_FS_NOE

-

SDMMC1_D1

-

LPTIM3_CH2

EVENTOUT

PC10

UART4_TX

TSC_G3_IO2

DCMI_D8/PSSI_D8

LPGPIO1_P8

SDMMC1_D2

SAI2_SCK_B

-

EVENTOUT

PC11

UART4_RX

TSC_G3_IO3

DCMI_D4/PSSI_D4

UCPD1_

FRSTX2

SDMMC1_D3

SAI2_MCLK_B

-

EVENTOUT

PC12

UART5_TX

TSC_G3_IO4

DCMI_D9/PSSI_D9

LPGPIO1_P10

SDMMC1_CK

SAI2_SD_B

-

EVENTOUT

PC13

-

-

-

-

-

-

-

EVENTOUT

PC14

-

-

-

-

-

-

-

EVENTOUT

PC15

-

-

-

-

-

-

-

EVENTOUT

Table 28. Alternate function AF8 to AF15

(1)

 (continued)

Port

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

LPUART1/

SDMMC1/

UART4/5

CAN1/TSC

CRS/DCMI/

OCTOSPIM_P1/2/

OTG_FS

LPGPIO1/
SDMMC2/

UCPD1/FMC

COMP1/2/FMC/

SDMMC1/2

LPTIM2/4/

SAI1/2

LPTIM2/3/

TIM2/15/16/17

EVENTOUT

STM32U575RGT6-html.html

Pin
out
, pin des

c

ript
io

n and alt

e

rna
te

 func
tions

ST
M32

U

57

5x

x

1

44/346

DS137

37 Rev 10

Port D

PD0

-

FDCAN1_RX

-

-

FMC_D2/FMC_

AD2

-

-

EVENTOUT

PD1

-

FDCAN1_TX

-

-

FMC_D3/FMC_

AD3

-

-

EVENTOUT

PD2

UART5_RX

TSC_SYNC

DCMI_D11/

PSSI_D11

LPGPIO1_P7

SDMMC1_CMD

LPTIM4_ETR

-

EVENTOUT

PD3

-

-

OCTOSPIM_

P2_NCS

-

FMC_CLK

-

-

EVENTOUT

PD4

-

-

OCTOSPIM_P1_IO4

-

FMC_NOE

-

-

EVENTOUT

PD5

-

-

OCTOSPIM_P1_IO5

-

FMC_NWE

-

-

EVENTOUT

PD6

-

-

OCTOSPIM_P1_IO6

SDMMC2_CK

FMC_NWAIT

SAI1_SD_A

-

EVENTOUT

PD7

-

-

OCTOSPIM_P1_IO7

SDMMC2_CMD

FMC_NCE/

FMC_NE1

LPTIM4_OUT

-

EVENTOUT

PD8

-

-

DCMI_HSYNC/

PSSI_DE

-

FMC_D13/FMC

_AD13

-

-

EVENTOUT

PD9

-

-

DCMI_PIXCLK/

PSSI_PDCK

-

FMC_D14/FMC

_AD14

SAI2_MCLK_A

LPTIM3_IN1

EVENTOUT

PD10

-

TSC_G6_IO1

-

-

FMC_D15/FMC

_AD15

SAI2_SCK_A

LPTIM3_ETR

EVENTOUT

PD11

-

TSC_G6_IO2

-

-

FMC_CLE/

FMC_A16

SAI2_SD_A

LPTIM2_ETR

EVENTOUT

PD12

-

TSC_G6_IO3

-

-

FMC_ALE/

FMC_A17

SAI2_FS_A

LPTIM2_IN1

EVENTOUT

PD13

-

TSC_G6_IO4

-

LPGPIO1_P6

FMC_A18

LPTIM4_IN1

LPTIM2_CH1

EVENTOUT

PD14

-

-

-

-

FMC_D0/FMC_

AD0

-

LPTIM3_CH1

EVENTOUT

PD15

-

-

-

-

FMC_D1/FMC_

AD1

-

LPTIM3_CH2

EVENTOUT

Table 28. Alternate function AF8 to AF15

(1)

 (continued)

Port

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

LPUART1/

SDMMC1/

UART4/5

CAN1/TSC

CRS/DCMI/

OCTOSPIM_P1/2/

OTG_FS

LPGPIO1/
SDMMC2/

UCPD1/FMC

COMP1/2/FMC/

SDMMC1/2

LPTIM2/4/

SAI1/2

LPTIM2/3/

TIM2/15/16/17

EVENTOUT

STM32U575RGT6-html.html

STM32

U

575
xx

Pinout

p

in de

sc

rip
tion an

d alter

n

at

e fu

nct
io

n

s

DS137

37 Rev 10

1

45/346

Port E

PE0

-

-

DCMI_D2/PSSI_D2

LPGPIO1_P13

FMC_NBL0

-

TIM16_CH1

EVENTOUT

PE1

-

-

DCMI_D3/PSSI_D3

-

FMC_NBL1

-

TIM17_CH1

EVENTOUT

PE2

-

TSC_G7_IO1

-

LPGPIO1_P14

FMC_A23

SAI1_MCLK_A

-

EVENTOUT

PE3

-

TSC_G7_IO2

-

LPGPIO1_P15

FMC_A19

SAI1_SD_B

-

EVENTOUT

PE4

-

TSC_G7_IO3

DCMI_D4/PSSI_D4

-

FMC_A20

SAI1_FS_A

-

EVENTOUT

PE5

-

TSC_G7_IO4

DCMI_D6/PSSI_D6

-

FMC_A21

SAI1_SCK_A

-

EVENTOUT

PE6

-

-

DCMI_D7/PSSI_D7

-

FMC_A22

SAI1_SD_A

-

EVENTOUT

PE7

-

-

-

-

FMC_D4/FMC_

AD4

SAI1_SD_B

-

EVENTOUT

PE8

-

-

-

-

FMC_D5/FMC_

AD5

SAI1_SCK_B

-

EVENTOUT

PE9

-

-

OCTOSPIM_P1_NC

LK

-

FMC_D6/FMC_

AD6

SAI1_FS_B

-

EVENTOUT

PE10

-

TSC_G5_IO1

OCTOSPIM_P1_CLK

-

FMC_D7/FMC_

AD7

SAI1_MCLK_B

-

EVENTOUT

PE11

-

TSC_G5_IO2

OCTOSPIM_

P1_NCS

-

FMC_D8/FMC_

AD8

-

-

EVENTOUT

PE12

-

TSC_G5_IO3

OCTOSPIM_P1_IO0

-

FMC_D9/FMC_

AD9

-

-

EVENTOUT

PE13

-

TSC_G5_IO4

OCTOSPIM_P1_IO1

-

FMC_D10/FMC

_AD10

-

-

EVENTOUT

PE14

-

-

OCTOSPIM_P1_IO2

-

FMC_D11/FMC

_AD11

-

-

EVENTOUT

PE15

-

-

OCTOSPIM_P1_IO3

-

FMC_D12/FMC

_AD12

-

-

EVENTOUT

Table 28. Alternate function AF8 to AF15

(1)

 (continued)

Port

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

LPUART1/

SDMMC1/

UART4/5

CAN1/TSC

CRS/DCMI/

OCTOSPIM_P1/2/

OTG_FS

LPGPIO1/
SDMMC2/

UCPD1/FMC

COMP1/2/FMC/

SDMMC1/2

LPTIM2/4/

SAI1/2

LPTIM2/3/

TIM2/15/16/17

EVENTOUT

STM32U575RGT6-html.html

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Port F

PF0

-

-

-

-

FMC_A0

-

-

EVENTOUT

PF1

-

-

-

-

FMC_A1

-

-

EVENTOUT

PF2

-

-

-

-

FMC_A2

-

-

EVENTOUT

PF3

-

-

-

-

FMC_A3

-

-

EVENTOUT

PF4

-

-

-

-

FMC_A4

-

-

EVENTOUT

PF5

-

-

-

-

FMC_A5

-

-

EVENTOUT

PF6

-

-

OCTOSPIM_P1_IO3

-

-

SAI1_SD_B

-

EVENTOUT

PF7

-

FDCAN1_RX

OCTOSPIM_P1_IO2

-

-

SAI1_MCLK_B

-

EVENTOUT

PF8

-

FDCAN1_TX

OCTOSPIM_P1_IO0

-

-

SAI1_SCK_B

-

EVENTOUT

PF9

-

-

OCTOSPIM_P1_IO1

-

-

SAI1_FS_B

TIM15_CH1

EVENTOUT

PF10

-

-

DCMI_D11/

PSSI_D11

-

-

SAI1_D3

TIM15_CH2

EVENTOUT

PF11

-

-

DCMI_D12/

PSSI_D12

-

-

LPTIM4_IN1

-

EVENTOUT

PF12

-

-

-

-

FMC_A6

LPTIM4_ETR

-

EVENTOUT

PF13

-

-

-

UCPD1_

FRSTX2

FMC_A7

LPTIM4_OUT

-

EVENTOUT

PF14

-

TSC_G8_IO1

-

-

FMC_A8

-

-

EVENTOUT

PF15

-

TSC_G8_IO2

-

-

FMC_A9

-

-

EVENTOUT

Table 28. Alternate function AF8 to AF15

(1)

 (continued)

Port

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

LPUART1/

SDMMC1/

UART4/5

CAN1/TSC

CRS/DCMI/

OCTOSPIM_P1/2/

OTG_FS

LPGPIO1/
SDMMC2/

UCPD1/FMC

COMP1/2/FMC/

SDMMC1/2

LPTIM2/4/

SAI1/2

LPTIM2/3/

TIM2/15/16/17

EVENTOUT

STM32U575RGT6-html.html

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Port G

PG0

-

TSC_G8_IO3

-

-

FMC_A10

-

-

EVENTOUT

PG1

-

TSC_G8_IO4

-

-

FMC_A11

-

-

EVENTOUT

PG2

-

-

-

-

FMC_A12

SAI2_SCK_B

-

EVENTOUT

PG3

-

-

-

-

FMC_A13

SAI2_FS_B

-

EVENTOUT

PG4

-

-

-

-

FMC_A14

SAI2_MCLK_B

-

EVENTOUT

PG5

LPUART1_CTS

-

-

-

FMC_A15

SAI2_SD_B

-

EVENTOUT

PG6

LPUART1_RTS/

LPUART1_DE

-

-

UCPD1_

FRSTX1

-

-

-

EVENTOUT

PG7

LPUART1_TX

-

-

UCPD1_

FRSTX2

FMC_INT

SAI1_MCLK_A

-

EVENTOUT

PG8

LPUART1_RX

-

-

-

-

-

-

EVENTOUT

PG9

-

-

-

-

FMC_NCE/

FMC_NE2

SAI2_SCK_A

TIM15_CH1N

EVENTOUT

PG10

-

-

-

-

FMC_NE3

SAI2_FS_A

TIM15_CH1

EVENTOUT

PG11

-

-

-

-

-

SAI2_MCLK_A

TIM15_CH2

EVENTOUT

PG12

-

-

-

-

FMC_NE4

SAI2_SD_A

-

EVENTOUT

PG13

-

-

-

-

FMC_A24

-

-

EVENTOUT

PG14

-

-

-

-

FMC_A25

-

-

EVENTOUT

PG15

-

-

DCMI_D13/

PSSI_D13

-

-

-

-

EVENTOUT

Table 28. Alternate function AF8 to AF15

(1)

 (continued)

Port

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

LPUART1/

SDMMC1/

UART4/5

CAN1/TSC

CRS/DCMI/

OCTOSPIM_P1/2/

OTG_FS

LPGPIO1/
SDMMC2/

UCPD1/FMC

COMP1/2/FMC/

SDMMC1/2

LPTIM2/4/

SAI1/2

LPTIM2/3/

TIM2/15/16/17

EVENTOUT

STM32U575RGT6-html.html

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Port H

PH0

-

-

-

-

-

-

-

EVENTOUT

PH1

-

-

-

-

-

-

-

EVENTOUT

PH2

-

-

-

-

-

-

-

EVENTOUT

PH3

-

-

-

-

-

-

-

EVENTOUT

PH4

-

-

PSSI_D14

-

-

-

-

EVENTOUT

PH5

-

-

DCMI_PIXCLK/

PSSI_PDCK

-

-

-

-

EVENTOUT

PH6

-

-

DCMI_D8/PSSI_D8

-

-

-

-

EVENTOUT

PH7

-

-

DCMI_D9/PSSI_D9

-

-

-

-

EVENTOUT

PH8

-

-

DCMI_HSYNC/

PSSI_DE

-

-

-

-

EVENTOUT

PH9

-

-

DCMI_D0/PSSI_D0

-

-

-

-

EVENTOUT

PH10

-

-

DCMI_D1/PSSI_D1

-

-

-

-

EVENTOUT

PH11

-

-

DCMI_D2/PSSI_D2

-

-

-

-

EVENTOUT

PH12

-

-

DCMI_D3/PSSI_D3

-

-

-

-

EVENTOUT

PH13

-

FDCAN1_TX

-

-

-

-

-

EVENTOUT

PH14

-

FDCAN1_RX

DCMI_D4/PSSI_D4

-

-

-

-

EVENTOUT

PH15

-

-

DCMI_D11/

PSSI_D11

-

-

-

-

EVENTOUT

Table 28. Alternate function AF8 to AF15

(1)

 (continued)

Port

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

LPUART1/

SDMMC1/

UART4/5

CAN1/TSC

CRS/DCMI/

OCTOSPIM_P1/2/

OTG_FS

LPGPIO1/
SDMMC2/

UCPD1/FMC

COMP1/2/FMC/

SDMMC1/2

LPTIM2/4/

SAI1/2

LPTIM2/3/

TIM2/15/16/17

EVENTOUT

STM32U575RGT6-html.html

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Port I

PI0

-

-

DCMI_D13/

PSSI_D13

-

-

-

-

EVENTOUT

PI1

-

-

DCMI_D8/PSSI_D8

-

-

-

-

EVENTOUT

PI2

-

-

DCMI_D9/PSSI_D9

-

-

-

-

EVENTOUT

PI3

-

-

DCMI_D10/

PSSI_D10

-

-

-

-

EVENTOUT

PI4

-

-

DCMI_D5/PSSI_D5

-

-

-

-

EVENTOUT

PI5

-

-

DCMI_VSYNC/

PSSI_RDY

-

-

-

-

EVENTOUT

PI6

-

-

DCMI_D6/PSSI_D6

-

-

-

-

EVENTOUT

PI7

-

-

DCMI_D7/PSSI_D7

-

-

-

-

EVENTOUT

1. For AF0 to AF7 refer to the previous table.

Table 28. Alternate function AF8 to AF15

(1)

 (continued)

Port

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

LPUART1/

SDMMC1/

UART4/5

CAN1/TSC

CRS/DCMI/

OCTOSPIM_P1/2/

OTG_FS

LPGPIO1/
SDMMC2/

UCPD1/FMC

COMP1/2/FMC/

SDMMC1/2

LPTIM2/4/

SAI1/2

LPTIM2/3/

TIM2/15/16/17

EVENTOUT

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DS13737 Rev 10

5 Electrical 

characteristics

5.1 Parameter 

conditions

Unless otherwise specified, all voltages are referenced to V

SS

.

5.1.1 

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst 
conditions of ambient temperature, supply voltage and frequencies by tests in production on 
100% of the devices with an ambient temperature at T

A

 = 25 °C and T

A

 = T

A

max (given by 

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics 
are indicated in the table footnotes, and are not tested in production. Based on 
characterization, the minimum and maximum values refer to sample tests and represent the 
mean value plus or minus three times the standard deviation (mean ±3

σ

).

5.1.2 Typical 

values

Unless otherwise specified, typical data are based on T

A

 = 25 °C, V

DD

 = V

DDA

 = 3 V. 

They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from 
a standard diffusion lot over the full temperature range and supply voltage range, where 
95% of the devices have an error less than or equal to the value indicated

 

(mean ±2

σ

)

.

5.1.3 Typical 

curves

Unless otherwise specified, all typical curves are given only as design guidelines and are 
not tested.

5.1.4 Loading 

capacitor

The loading conditions used for pin parameter measurement are shown in 

Figure 22

.

5.1.5 

Pin input voltage

The input voltage measurement on a pin of the device is described in 

Figure 23

.

          

5.1.6 

Power supply scheme

Each power supply pair (such as V

DD

/V

SS

 or V

DDA

/V

SSA

) must be decoupled with filtering 

ceramic capacitors as shown in 

Figure 24

 and 

Figure 25

. These capacitors must be placed 

Figure 22. Pin loading conditions

Figure 23. Pin input voltage

MSv68045V1

MCU pin

C = 50 pF

MSv68046V1

MCU pin

V

IN

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305

as close as possible to, or below, the appropriate pins on the underside of the PCB to 
ensure the proper functionality of the device.

Figure 24. STM32U575xx power supply scheme (without SMPS)

Caution:

If there are two VCAP pins (UFBGA169 package), each pin must be connected to a 2.2 µF 
(typical) capacitor.

The external capacitor on VCAP pin requires the following characteristics:

C

OUT

 = 4.7 µF or 2 × 2.2 µF ±20%

C

OUT

 ESR < 20 m

 at 3 MHz

C

OUT

 rated voltage 

 10 V

MSv64358V4

V

DDIO2

V

DD

Level shifter

I/O

logic

Kernel logic

(CPU, digital

and 

memories)

Backup circuitry

(LSE, RTC, TAMP

backup registers, 

backup SRAM)

IN

OUT

LDO 

regulator

GPIOs

1.65 – 3.6 V

IN

OUT

GPIOs

n x 100 nF

+ 1 x 10 μF

m x 100 nF

Level shifter

I/O

logic

+ 4.7 μF                                                                

m x VDDIO2

m x VSS

n x VSS

n x VDD

VBAT

V

CORE

Power switch

V

DDIO2

V

DDIO1

ADCs/
DACs/

OPAMPs/

COMPs/

VREFBUF

V

REF+

V

REF-

V

DDA

100 nF

+1 μF

VDDA

VSSA

V

REF

100 nF+ 1 μF

V

CORE

C

OUT

 = 4.7 μF

VCAP

VDDUSB

V

DDUSB

100 nF

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DS13737 Rev 10

Figure 25. STM32U575xQ power supply scheme (with SMPS)

Note:

SMPS and LDO regulators provide, in a concurrent way, the V

CORE

 supply depending on 

application requirements. However, only one of them is active at the same time. When 
SMPS is active, it feeds the V

CORE

 on the two VDD11 pins supplied by the filtered SMPS 

VLXSMPS output pin. When LDO is active, it supplies the V

CORE

 and regulates it using the 

same capacitors on VDD11 pins. It is recommended to add a decoupling capacitor of 100 nF 
near each VDD11 pin/ball, but it is not mandatory.

MSv64359V4

V

DDIO2

V

DD

Kernel logic 

(CPU, digital 

and memories)

Level shifter

I/O

logic

Backup circuitry

(LSE, RTC, TAMP,

backup registers, 

backup SRAM)

IN

OUT

GPIOs

1.65 – 3.6 V

IN

OUT

GPIOs

n x 100 nF

+ 10 μF

m x100 nF

Level shifter

I/O

logic

+ 4.7 μF                                                                                                                                

m x VDDIO2

m x VSS

n x VSS

n x VDD

VBAT

V

CORE

Power switch

V

DDIO2

V

DDIO1

ADCs/
DACs/

OPAMPs/

COMPs/

VREFBUF

V

REF+

V

REF-

V

DDA

100 nF

+ 1 μF

VDDA

VSSA

V

REF

100 nF+ 1 μF

VSSSMPS

2 x VDD11

VLXSMPS

VDDSMPS

V

DD

L = 2.2 μH

C

OUT

 = 2 x 2.2 μF

C

IN

 = 10 μF

SMPS ON

SMPS OFF

LDO

SMPS

VDDUSB

100 nF

Voltage regulator

V

DDUSB

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The external capacitors on VDD11 pins require the following characteristics:

C

OUT

 = 2 × 2.2 µF ±20%

C

OUT

 ESR < 20 m

 at 3 MHz

C

OUT

 rated voltage 

 10 V

The external capacitor on VDDSMPS pin requires the following characteristics:

C

IN 

= 10 µF ±20%

C

IN

 ESR < 10 m

 at 3 MHz

C

IN

 rated voltage 

 10 V

The external inductance between VLXSMPS and VDD11 requires the following 
characteristics:

L = 2.2 µH ±20%

L I

SAT

 > 0.5 A

L DCR < 200 m

5.1.7 Current 

consumption 

measurement

The I

DD

 parameters given in various tables in the next sections, represent the total MCU 

consumption including the current supplying V

DD

, V

DDIO2

, V

DDA

, V

DDUSB

, V

BAT

 and 

V

DDSMPS

 (if the device embeds the SMPS).

Figure 26. Current consumption measurement

5.2 

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in 

Table 29

Table 30

 an

Table 31

 

may cause permanent damage to the device. These are stress ratings only and the 
functional operation of the device at these conditions is not implied. Exposure to maximum 
rating conditions for extended periods may affect device reliability. Device mission profile 
(application conditions) is compliant with JEDEC JESD47 qualification standard, extended 
mission profiles are available on demand.

MSv62920V2

I

DD

_V

BAT

I

DD

V

BAT

V

DD

V

DDA

V

DDUSB

V

DDSMPS

V

DDIO2

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DS13737 Rev 10

          

          

Table 29. Voltage characteristics

(1)(2)

 

Symbol

Ratings

Min

Max

Unit

V

DDX

 - V

SS

External main supply voltage (including 
V

DDSMPS

, V

DDA

, V

DDUSB

, V

BAT

, V

REF+

)

-0.3

4.0

V

V

DDIOx

(3)

 - V

SS

I/O supply when HSLV = 0

-0.3

4.0

I/O supply when HSLV = 1

-0.3

2.75

V

IN

(4)

Input voltage on FT_xx pins except 
FT_c pins

V

SS

 - 0.3

Min (min (V

DD

, V

DDA

, V

DDUSB

, V

DDIO2

+ 4.0, 6.0)

(5)(6)

Input voltage on FT_t pins in 
V

BAT 

mode

V

SS

 - 0.3

Min (min (V

BAT

, V

DDA

, V

DDUSB

V

DDIO2

) + 4.0, 6.0) 

(5)(6)

V

IN

(4)

Input voltage on FT_c pins

V

SS

 - 0.3

5.5

V

Input voltage on any other pins

V

SS

 - 0.3

4.0

V

REF+

 - V

DDA

Allowed voltage difference for 
V

REF+

 > V

DDA

-

0.4

|

V

DDx

|

Variations between different VDDx 
power pins of the same domain

-

50.0

mV

|V

SSx

-V

SS

|

Variations between all the different 
ground pins

(7)

-

50.0

1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must 

always be connected to the external power supply, in the permitted range.

2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For 

instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

3. V

DDIO1

 or V

DDIO2 

or V

SW

, V

DDIO1

 = V

DD

.

4. V

IN

 maximum must always be respected. Refer to 

Table 30

 for the maximum allowed injected current values.

5. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.

6. This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.

7. Including VREF- pin.

Table 30. Current characteristics 

Symbol

Ratings

Max

Unit

IV

DD

Total current into sum of all V

DD

 power lines (source)

(1)

200

mA

IV

SS

Total current out of sum of all V

SS

  ground lines (sink)

(1)

200

IV

DD

Maximum current into each VDD power pin (source)

(1)

100

IV

SS

Maximum current out of each VSS ground pin (sink)

(1)

100

I

IO

Output current sunk by any I/O and control pin

20

Output current sourced by any I/O and control pin

20

I

(PIN)

Total output current sunk by sum of all I/Os and control pins

(2)

120

Total output current sourced by sum of all I/Os and control pins

(2)

120

I

INJ(PIN)

(3)(4)

Injected current on FT_xx, TT_xx, RST pins

-5/+0

|I

INJ(PIN)

|

Total injected current (sum of all I/Os and control pins)

(5)

±25

1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must 

always be connected to the external power supplies, in the permitted range.

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2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be 

sunk/sourced between two consecutive power supply pins, referring to high pin count QFP packages.

3. Positive injection (when V

IN 

> V

DDIOx

) is not possible on these I/Os and does not occur for input voltages lower than the 

specified maximum value.

4. A negative injection is induced by V

IN

 < V

SS

. I

INJ(PIN)

 must never be exceeded. Refer also to 

Table 29

 for the minimum 

allowed input voltage values.

5. When several inputs are submitted to a current injection, the maximum 

|I

INJ(PIN)

 is the absolute sum of the negative 

injected currents (instantaneous values).

Table 31. Thermal characteristics 

Symbol

Ratings

 Value

Unit

T

STG

Storage temperature range

–65 to +150

°C

T

J

Maximum junction temperature

140

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5.3 Operating 

conditions

5.3.1 

General operating conditions

          

Table 32. General operating conditions 

Symbol

Parameter

 Conditions

Min

Typ

Max

Unit

V

DD

Standard operating 
voltage

IO_VDD_HSLV

(1)

 = 0

1.71

(2)

-

3.6

V

IO_VDD_HSLV = 1

1.71

(2)

-

2.7

V

DDSMPS

Supply voltage for 
the internal SMPS 
step-down 
converter

-

V

DD

V

DDIO2

Supply voltage for 
PG[15:2] I/Os

At least one I/O in 
PG[15:2] used, 
IO_VDDIO2_HSLV = 0

1.08

-

3.6

At least one I/O in 
PG[15:2] used, 
IO_VDDIO2_HSLV = 1

1.08

-

2.7

PG[15:2] I/Os not used

0

-

3.6

V

DDUSB

USB supply voltage

USB used

3.0

-

3.6

USB not used

0

-

3.6

V

DDA

Analog supply 
voltage

COMP used

1.58

-

3.6

DAC or OPAMP used

1.60

3.6

ADC used

1.62

-

3.6

VREFBUF used 
(normal mode)

1.8

-

3.6

ADC, DAC, COMP, 
OPAMP, and VREFBUF 
not used

0

-

3.6

V

BAT

Backup domain 
supply voltage

-

1.65

(3)

-

3.6

V

IN

I/O input voltage

All I/Os except FT_c and 
TT_xx pins

-0.3

-

Min(min(V

DD

, V

DDA

, V

DDUSB

V

DDIO2

) +3.6, 5.5)

(4)(5)

V

Input voltage on FT_t pins 
in V

BAT

 mode

-0.3

-

Min(min(V

BAT

, V

DDA

V

DDUSB, 

V

DDIO2

)+ 3.6, 

5.5)

(4)(5)

FT_c I/Os

-0.3

-

5.0

TT_xx I/Os

-0.3

-

V

DDIOx

 + 0.3

I

IO_SW

Sum of output 
current sourced by 
all I/Os powered by 
V

SW

(6)

-

-

-

3

mA

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V

CORE

Internal regulator 
ON

Range 1

1.15

1.21

1.27

V

Range 2

1.05

1.1

1.15

Range 3

0.95

1.0

1.05

Range 4

0.81

0.9

0.99

f

HCLK

AHB clock 
frequency

Range 1

-

-

160

MHz

Range 2

-

-

110

Range 3

-

-

55

Range 4

-

-

25

f

PCLKx 

(x = 1, 2, 3)

APB1, APB2, 
APB3 clock 
frequency

Range 1

-

-

160

Range 2

-

-

110

Range 3

-

-

55

Range 4

-

-

25

P

D

Power dissipation 
at T

A

 

= 85 °C 

for suffix 6

(7)

LQFP48

See 

Section 6.9: Package thermal 

characteristics

 for application appropriate 

thermal resistance and package. The power 

dissipation is then calculated according to 

ambient temperature (T

A

) and maximum 

junction temperature (T

J

) and selected thermal 

resistance.

mW

UFQFPN48

LQFP64

WLCSP90

LQFP100

UFBGA132

LQFP144

UFBGA169

P

D

Power dissipation 
at T

A

 = 125 °C 

for suffix 3

(7)

LQFP48

See 

Section 6.9: Package thermal 

characteristics

 for application appropriate 

thermal resistance and package. The power 

dissipation is then calculated according 

ambient temperature (T

A

) and maximum 

junction temperature (T

J

) and selected thermal 

resistance.

UFQFPN48

LQFP64

WLCSP90

LQFP100

UFBGA132

LQFP144

UFBGA169

Table 32. General operating conditions (continued)

Symbol

Parameter

 Conditions

Min

Typ

Max

Unit

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DS13737 Rev 10

5.3.2 Operating 

conditions at power-up/power-down

The parameters given in the table below are derived from tests performed under the 
ambient temperature condition summarized in 

Table 32

.

          

T

A

Ambient 
temperature 
for suffix 6

Maximum power 
dissipation

–40

-

85

°C

Low-power dissipation

(8)

–40

-

105

Ambient 
temperature 
for suffix 3

Maximum power 
dissipation 

–40

-

125

Low-power dissipation

(8)

–40

-

130

T

J

Junction 
temperature range

Suffix 6 version

–40 

-

105

Suffix 3 version

–40 

-

130

1. HSLV means high-speed low-voltage mode (refer to the product reference manual).

2. When RESET is released, the functionality is guaranteed down to V

BORx

 min.

3. In V

BAT 

mode, the functionality is guaranteed down to V

BOR_VBAT

 min.

4. This formula has to be applied only on the power supplies related to the I/O structure described by the pin definition table. 

The maximum I/O input voltage is the smallest value between Min (V

DD

, V

DDA

, V

DDUSB, 

V

DDIO2

)+3.6 V, and 5.5V.

5. For operation with voltage higher than Min (V

DD

, V

DDA

, V

DDUSB, 

V

DDIO2

) +0.3 V, the internal pull-up and pull-down resistors 

must be disabled.

6. The I/Os powered by V

SW

 are: 

- PC13, PC14, PC15 when V

DD

 is present,

- PC13, PC14, PC15, and all FT_t I/Os in V

BAT

 mode.

7. If T

A

 is lower, higher P

D

 values are allowed as long as T

J

 does not exceed T

max (see 

Section 6.9: Package thermal 

characteristics

).

8. In low-power dissipation state, T

A

 can be extended to this range as long as T

J

 does not exceed T

max (see 

Section 6.9: 

Package thermal characteristics

).

Table 32. General operating conditions (continued)

Symbol

Parameter

 Conditions

Min

Typ

Max

Unit

Table 33. Operating conditions at power-up/power-down 

Symbol

Parameter

Conditions

Min

Max

Unit

t

VDD

V

DD

 rise-time rate

-

0

µs/V

V

DD

 fall-time rate

ULPMEN = 0 (default value)

20

Standby mode, BOR level 0 selected 
with ULPMEN = 1

250

ms/V

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5.3.3 

Embedded reset and power control block characteristics

The parameters given in the table below are derived from tests performed under the 
ambient temperature conditions summarized in 

Table 32

.

          

Table 34. Embedded reset and power control block characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t

RSTTEMPO

(2)

Reset temporization after BOR0 is 
detected

V

DD 

rising

-

-

900

μ

s

V

BOR0

Brownout reset threshold 0

Rising edge

1.6

1.66

1.71

V

Falling edge, range 1, 2, 3

1.58

1.64

1.69

Falling edge, range 4 and 
low-power modes

1.58

1.64

1.69

V

BOR1

Brownout reset threshold 1

Rising edge

1.98

2.08

2.17

Falling edge

1.9

2.00

2.1

V

BOR2

Brownout reset threshold 2

Rising edge

2.18

2.29

2.39

Falling edge

2.08

2.18

2.25

V

BOR3

Brownout reset threshold 3

Rising edge

2.48

2.59

2.7

Falling edge

2.39

2.5

2.61

V

BOR4

Brownout reset threshold 4

Rising edge

2.76

2.88

3.0

Falling edge

2.67

2.79

2.9

V

PVD0

Programmable voltage detector 
threshold 0

Rising edge

2.03

2.13

2.23

Falling edge

1.93

2.03

2.12

V

PVD1

PVD threshold 1

Rising edge

2.18

2.29

2.39

Falling edge

2.08

2.18

2.28

V

PVD2

PVD threshold 2

Rising edge

2.33

2.44

2.55

Falling edge

2.23

2.34

2.44

V

PVD3

PVD threshold 3

Rising edge

2.47

2.59

2.7

Falling edge

2.39

2.50

2.61

V

PVD4

PVD threshold 4

Rising edge

2.6

2.72

2.83

Falling edge

2.5

2.62

2.73

V

PVD5

PVD threshold 5

Rising edge

2.76

2.88

3.0

Falling edge

2.66

2.78

2.9

V

PVD6

PVD threshold 6

Rising edge

2.83

2.96

3.08

Falling edge

2.76

2.88

3.0

V

hyst_BOR0

Hysteresis voltage of BOR0

-

-

20

-

mV

V

hyst_BOR_PVD

Hysteresis voltage of BOR 
(except BOR0) and PVD

-

-

80

-

t

BOR0 _sampling

BOR0 sampling period

ULPMEN = 1

-

30

55

ms

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DS13737 Rev 10

5.3.4 SMPS 

characteristics

          

I

DD_BOR0

(2)

Additional BOR0 consumption if 
ULPMEN = 0 versus ULPMEN = 1

Standby mode

-

60

-

nA

I

DD_BOR_PVD

(2)

BOR

(3)

 (except BOR0) and PVD 

consumption from V

DD

(4)

-

-

1

1.5

µA

 V

BOR_VBAT

V

BAT

 brownout reset threshold

-

1.58

-

1.65

V

t

VBAT_BOR

_sampling

V

BAT

 BOR sampling period 

in V

BAT

 mode

MONEN = 0

(5)

-

0.5

2.5

s

V

AVM1

V

DDA

 voltage monitor 1 threshold

Rising edge

1.61

1.68

1.75

V

Falling edge

1.58

1.65

1.71

V

AVM2

V

DDA

 voltage monitor 2 threshold

Rising edge

1.77

1.86

1.95

Falling edge

1.73

1.82

1.9

V

IO2VM

V

DDIO2

 voltage monitor threshold

-

0.96

1.01

1.05

V

UVM

V

DDUSB

 voltage monitor threshold

-

1.15

1.22

1.28

V

hyst_AVM

Hysteresis of V

DDA

 voltage monitor

-

-

40

-

mV

I

DD_VM

(2)

Voltage monitor consumption from 
V

DD

 (AVM1, AVM2, IO2VM or UVM 

single instance)

-

-

0.4

0.6

µA

I

DD_AVM_A

(2)

V

DDA

 voltage monitor consumption 

from V

DDA

 (resistor bridge)

-

-

1.25

1.85

1. Evaluated by characterization and not tested in production, unless otherwise specified.

2. Specified by design. Not tested in production

3. BOR0 is enabled in all modes (except Shutdown), and its consumption is therefore included in the supply current 

characteristics tables.

4. This is also the consumption saved in Standby mode when ULPMEN = 1.

5. V

BAT

 brownout reset monitoring is discontinuous when MONEN = 0 in PWR_BDCR1, and is continuous when MONEN = 1.

Table 34. Embedded reset and power control block characteristics

(1)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 35. SMPS characteristics 

Symbol

Parameter

Conditions

Typ

Unit

Freq

Switching frequency (range 1, 2, 3)

(1)

V

DD 

> 1.9 V

3

MHz

V

DD

 < 1.9 V

1.5

1. The SMPS is asynchronous in range 4 and low-power modes.

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5.3.5 Embedded 

voltage 

reference

The parameters given in the table below are derived from tests performed under the 
ambient temperature and supply voltage conditions summarized in 

Table 32

.

           

Table 36. Embedded internal voltage reference 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

REFINT

(1)

Internal reference voltage

Range 1, 2, 3

1.175 1.215 1.255

V

Range 4 and 
low-power modes

1.170 1.215 1.260

t

S_vrefint

(2)(3)

ADC sampling time when reading 
the internal reference voltage

-

12.65

-

-

µs

t

start_vrefint

(3)

Start time of reference voltage buffer 
when the ADC is enabled

-

-

4

6

 I

DD(VREFINTBUF)

(3)

V

REFINT

 buffer consumption from 

V

DD

 when converted by the ADC

-

-

1.5

2.1

µA

V

REFINT

(4)

Internal reference voltage spread 
over the temperature range

V

DD

 = 3 V

-

6

11.5

mV

T

Coeff

(4)

Average temperature coefficient

–40°C < T

J

 < +130 °C

-

40

125

ppm/°C

A

Coeff

(3)

Long term stability

1000 hours, T

= 25 °C

-

400

1000

ppm

V

DDCoeff

(4)

Average voltage coefficient

3.0 V 

 V

DD

 

 3.6 V

-

500

2900

ppm/V

V

REFINT_DIV1

(3)

1/4 reference voltage

-

24

25

26

V

REFINT

V

REFINT_DIV2

(3)

1/2 reference voltage

-

49

50

51

V

REFINT_DIV3

(3)

3/4 reference voltage

-

74

75

76

1. V

REFINT

 does not take into account package and soldering effects.

2. The shortest sampling time for the application can be determined by multiple iterations.

3. Specified by design. Not tested in production.

4. Evaluated by characterization. Not tested in production. 

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DS13737 Rev 10

Figure 27. V

REFINT

 versus temperature

5.3.6 

Supply current characteristics

The current consumption is a function of several parameters and factors such as the 
operating voltage, ambient temperature, I/O pin loading, device software configuration, 
operating frequencies, I/O pin switching rate, program location in memory and executed 
binary code.

The current consumption is measured as described in 

Section 5.1.7: Current consumption 

measurement

.

Typical and maximum current consumption

The MCU is placed under the following conditions:

All I/O pins are in analog input mode.

All peripherals are disabled except when explicitly mentioned.

The Flash memory access time is adjusted with the minimum wait-state number, 
depending on the f

HCLK

 frequency (refer to the tables “Number of wait states according 

to CPU clock (HCLK) frequency” available in the product reference manual).

When the peripherals are enabled, f

PCLK

 = f

HCLK

.

The voltage scaling range is adjusted to f

HCLK

 frequency as follows:

Voltage range 1 for 110 MHz < f

HCLK

 

 160 MHz

Voltage range 2 for 55 MHz < f

HCLK

 

 110 MHz

Voltage range 3 for 25 MHz < f

HCLK

 

 55 MHz

Voltage range 4 for f

HCLK

 

 25 MHz

The parameters given in the tables below are derived from tests performed under ambient 
temperature and supply voltage conditions summarized in 

Table 32

.

MSv69159V1

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Table 37. Current consumption in Run mode on LDO, code with data processing

running from Flash memory, ICACHE ON (1-way), prefetch ON

(1)

 

Symbol

Parameter

Conditions

Typ

Max

(2)

Unit

-

Voltage 

scaling

f

HCLK 

(MHz)

25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

I

DD

(Run)

Supply 
current in 
Run mode

f

HCLK

 = f

MSI

,

all peripherals and AHB/APB 
disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 4

24

1.75

2.10

3.10

4.65

7.70

2.60

3.40

6.40

12.00 21.00

mA

16

1.30

1.65

2.65

4.20

7.25

2.10

2.90

5.90

11.00 20.00

12

1.05

1.40

2.40

3.95

7.00

1.80

2.70

5.60

11.00 20.00

4

0.49

0.82

1.85

3.40

6.40

1.20

2.00

5.00

9.80

19.00

2

0.37

0.70

1.70

3.25

6.30

1.10

1.90

4.90

9.60

19.00

1

0.30

0.63

1.65

3.20

6.20

0.94

1.80

4.80

9.60

19.00

0.4

0.26

0.59

1.60

3.15

6.15

0.89

1.80

4.80

9.50

19.00

0.1

0.24

0.57

1.55

3.15

6.15

0.87

1.80

4.70

9.50

19.00

f

HCLK

 = PLL on HSE 16 MHz in 

bypass mode,
all peripherals and AHB/APB 
disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 1

160

13.50 14.50 16.00 18.50 23.50 17.00 19.00 26.00 37.00 57.00

140

12.00 12.50 14.50 17.00 21.50 15.00 17.00 24.00 35.00 55.00

120

10.50 11.00 13.00 15.50 20.00 14.00 15.00 23.00 33.00 53.00

Range 2

110

8.80

9.35 10.50 13.00 16.50 11.00 13.00 18.00 26.00 41.00

72

6.00

6.50 10.00 10.00 14.00

7.80

9.30 15.00 23.00 38.00

64

5.40

5.95

9.50

9.50

13.50

7.10

8.70 14.00 22.00 38.00

f

HCLK

 = f

HSE 

bypass mode,

all peripherals and AHB/APB 
disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 3

55

4.25

4.65

5.90

7.75

11.50

5.60

6.70

11.00 17.00 29.00

32

2.70

3.10

4.30

6.10

9.60

3.80

5.00

8.80

15.00 27.00

1. The current consumption from SRAM is similar.

2. Evaluated by characterization. Not tested in production. 

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Table 38. Current consumption in Run mode on SMPS, code with data processing

running from Flash memory, ICACHE ON (1-way), prefetch ON

(1)

 

Symbol

Parameter

Conditions

Typ at V

DD

 = 1.8 V

Max at 1.71 V 

 V

DD

 

 3.6 V

(2)(3)

Unit

-

Voltage 

scaling

f

HCLK

 

(MHz)

25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

I

DD

(Run)

Supply 
current in 
Run mode

f

HCLK

 = f

MSI

,

all peripherals and AHB/APB 
disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 4

24

1.15

1.35

2.05

3.10

5.20

2.30

2.40

4.50

7.80

15.00

mA

16

0.88

1.10

1.75

2.80

4.90

1.60

2.00

4.20

7.50

15.00

12

0.62

0.97

1.60

2.65

4.70

1.30

1.80

4.00

7.30

14.00

4

0.34

0.56

1.20

2.20

4.40

0.77

1.40

3.50

6.80

14.00

2

0.22

0.46

1.15

2.20

4.25

0.64

1.30

3.50

6.80

14.00

1

0.18

0.40

1.10

2.15

4.20

0.60

1.20

3.40

6.70

14.00

0.4

0.16

0.36

1.05

2.10

4.20

0.57

1.10

3.40

6.70

14.00

0.1

0.15

0.34

1.05

2.10

4.20

0.55

1.10

3.40

6.70

14.00

f

HCLK

 = PLL on HSE 16 MHz in 

bypass mode,
all peripherals and AHB/APB 
disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 1

160

10.50 11.00 12.50 14.50 18.00 14.00 15.00 21.00 28.00 44.00

140

9.30

9.85 11.00 13.00 16.50 13.00 14.00 19.00 27.00 42.00

120

8.50

9.05 10.50 12.50 16.50 11.00 13.00 18.00 26.00 42.00

Range 2

110

6.95

7.40

8.55

10.00 13.00

8.90

9.90 14.00 20.00 32.00

72

4.35

4.70

5.65

7.10

9.80

6.00

6.80 11.00 17.00 28.00

64

3.95

4.30

5.25

6.65

9.40

5.40

6.30 11.00 16.00 27.00

f

HCLK

 = f

HSE

 bypass mode,

all peripherals and AHB/APB 
disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 3

55

3.05

3.40

4.25

5.60

7.95

4.10

4.90

7.90

13.00 21.00

32

1.85

2.10

2.85

3.95

6.15

2.70

3.40

6.20

11.00 19.00

1. The current consumption from SRAM is similar.

2. Evaluated by characterization. Not tested in production.

3. The maximum value is at V

DD

 = 1.71 V in Run mode on SMPS.

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Table 39. Current consumption in Run mode on SMPS, code with data processing

running from Flash memory, ICACHE ON (1-way), prefetch ON, V

DD

 = 3.0 V

(1)

 

Symbol

Parameter

Conditions

Typ at V

DD

 = 3.0 V

Max at V

DD

 = 3.0 V

(2)

Unit

-

Voltage 

scaling

f

HCLK

 

(MHz)

25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

I

DD

(Run)

Supply 
current in 
Run mode

f

HCLK

 = f

MSI

,

all peripherals and AHB/APB 
disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 4

24

0.73

0.91

1.30

2.00

3.45

2.30

2.40

3.10

4.80

9.10

mA

16

0.60

0.71

1.15

1.80

3.25

1.60

1.90

2.70

4.60

8.80

12

0.45

0.65

1.05

1.70

3.15

1.30

1.60

2.60

4.50

8.70

4

0.23

0.38

0.82

1.50

2.80

0.60

0.97

2.30

4.30

8.40

2

0.17

0.31

0.74

1.40

2.85

0.49

0.84

2.20

4.20

8.40

1

0.15

0.29

0.73

1.40

2.80

0.46

0.81

2.20

4.20

8.40

0.4

0.13

0.27

0.72

1.40

2.75

0.44

0.79

2.20

4.20

8.30

0.1

0.12

0.26

0.72

1.35

2.75

0.44

0.78

2.20

4.10

8.30

f

HCLK

 = PLL on HSE 16 MHz in 

bypass mode,
all peripherals and AHB/APB 
disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 1

160

7.15

7.55

8.55

9.90

12.50 14.00 15.00 16.00 19.00 28.00

140

6.35

6.75

7.70

9.05

11.50 13.00 13.00 15.00 17.00 27.00

120

5.80

6.20

7.20

8.60

11.00 11.00 12.00 13.00 17.00 26.00

Range 2

110

4.40

4.70

5.40

6.35

8.20

8.90

9.20 11.00 13.00 19.00

72

3.05

3.35

4.05

5.10

7.00

6.00

6.20

7.40

11.00 18.00

64

2.80

3.10

3.80

4.80

6.70

5.40

5.70

6.90

11.00 18.00

f

HCLK

 = f

HSE

 bypass mode,

all peripherals and AHB/APB 
disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 3

55

2.20

2.45

3.05

3.95

5.55

4.00

4.40

5.40

7.90

14.00

32

1.40

1.60

2.15

2.95

4.50

2.60

3.00

4.30

6.80

13.00

1. The current consumption from SRAM is similar.

2. Evaluated by characterization. Not tested in production.

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Table 40. Typical current consumption in Run mode on LDO, with different codes

running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON 

Symbol

Parameter

Conditions

Typ

Unit

Typ

Unit

-

Voltage 

scaling

Code

1.8 V

3 V

3.3 V

1.8 V

3 V

3.3 V

I

DD

(Run)

Supply 
current in 
Run mode

f

HCLK 

= f

MSI 

= 24 MHz,

all peripherals disabled,
Flash bank 2 in power down,
SRAM2 enabled,
SRAM1, SRAM3, SRAM4 in 
power down

Range 4

Reduced Code

1.65

1.65

1.65

mA

68.8

68.8

68.8

µA/

MHz

CoreMark

1.55

1.60

1.60

64.6

66.7

66.7

SecureMark

1.80

1.80

1.80

75.0

75.0

75.0

Dhrystone 2.1

1.65

1.65

1.65

68.8

68.8

68.8

Fibonacci

1.30

1.30

1.30

54.2

54.2

54.2

while(1)

1.20

1.20

1.20

50.0

50.0

50.0

Table 41. Typical current consumption in Run mode on LDO, with different codes

running from Flash memory, ICACHE ON (1-way), prefetch ON

(1)

 

Symbol

Parameter

Conditions

Typ

Unit

Typ

Unit

-

Voltage 

scaling

Code

1.8 V

3 V

3.3 V

1.8 V

3 V

3.3 V

I

DD

(Run)

Supply 
current in 
Run mode

f

HCLK 

= f

MSI 

= 24 MHz,

all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 4

Reduced Code

1.75

1.75

1.75

mA

72.9

72.9

72.9

µA/

MHz

CoreMark

1.65

1.65

1.65

68.8

68.8

68.8

SecureMark

1.85

1.85

1.90

77.1

77.1

79.2

Dhrystone 2.1

1.75

1.75

1.75

72.9

72.9

72.9

Fibonacci

1.40

1.40

1.40

58.3

58.3

58.3

While(1)

1.30

1.30

1.30

54.2

54.2

54.2

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I

DD

(Run)

Supply 
current in 
Run mode

f

HCLK

 = f

PLL

 = 160 MHz,

PLL on HSE 16 MHz in bypass 
mode,
all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 1

Reduced Code

13.50

13.50

13.50

mA

84.4

84.4

84.4

µA/

MHz

CoreMark

13.50

13.50

13.50

84.4

84.4

84.4

SecureMark

15.00

15.00

15.00

93.8

93.8

93.8

Dhrystone 2.1

14.00

14.00

14.00

87.5

87.5

87.5

Fibonacci

10.50

10.50

10.50

65.6

65.6

65.6

While(1)

10.00

10.00

10.00

62.5

62.5

62.5

f

HCLK

 = f

PLL

 = 110 MHz,

PLL on HSE 16 MHz in bypass 
mode,
all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 2

Reduced Code

8.80

8.80

8.85

80.0

80.0

80.5

CoreMark

8.60

8.65

8.65

78.2

78.6

78.6

SecureMark

9.65

9.70

9.70

87.7

88.2

88.2

Dhrystone 2.1

9.05

9.05

9.10

82.3

82.3

82.7

Fibonacci

6.80

6.80

6.80

61.8

61.8

61.8

While(1)

6.55

6.55

6.60

59.5

59.5

60.0

f

HCLK

 = f

HSE

 = 55 MHz,

all peripherals disable,
Flash bank 2 in power down,
all SRAMs enabled

Range 3

Reduced Code

4.15

4.25

4.25

75.5

77.3

77.3

CoreMark

4.15

4.20

4.25

75.5

76.4

77.3

SecureMark

4.65

4.70

4.75

84.5

85.5

86.4

Dhrystone 2.1

4.35

4.40

4.40

79.1

80.0

80.0

Fibonacci

3.25

3.30

3.35

59.1

60.0

60.9

While(1)

3.05

3.10

3.15

55.5

56.4

57.3

1. The current consumption from SRAM is similar.

Table 41. Typical current consumption in Run mode on LDO, with different codes

running from Flash memory, ICACHE ON (1-way), prefetch ON

(1)

 (continued)

Symbol

Parameter

Conditions

Typ

Unit

Typ

Unit

-

Voltage 

scaling

Code

1.8 V

3 V

3.3 V

1.8 V

3 V

3.3 V

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Table 42. Typical current consumption in Run mode on SMPS, with different codes

running from Flash memory in low-power mode, ICACHE ON (1-way), prefetch ON 

Symbol

Parameter

Conditions

Typ

Unit

Typ

Unit

-

Voltage 

scaling

Code

1.8 V

3 V

3.3 V

1.8 V

3 V

3.3 V

I

DD

(Run)

Supply 
current in 
Run mode

f

HCLK 

= f

MSI 

= 24 MHz,

all peripherals disabled,
Flash bank 2 in power down,
SRAM2 enabled,
SRAM1, SRAM3, SRAM4 in 
power down

Range 4

Reduced Code

1.10

0.69

0.64

mA

45.8

28.5

26.5

µA/

MHz

CoreMark

1.05

0.68

0.61

43.8

28.3

25.4

SecureMark

1.20

0.79

0.72

50.0

32.9

30.0

Dhrystone 2.1

1.10

0.69

0.64

45.8

28.5

26.7

Fibonacci

0.89

0.59

0.51

37.1

24.4

21.3

while(1)

0.77

0.54

0.47

32.1

22.3

19.5

Table 43. Typical current consumption in Run mode on SMPS, with different codes

running from Flash memory, ICACHE ON (1-way), prefetch ON

(1)

 

Symbol

Parameter

Conditions

Typ

Unit

Typ

Unit

-

Voltage 

scaling

Code

1.8 V

3 V

3.3 V

1.8 V

3 V

3.3 V

I

DD

(Run)

Supply 
current in 
Run mode

f

HCLK 

= f

MSI 

= 24 MHz,

all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 4

Reduced Code

1.15

0.73

0.68

mA

47.9

30.2

28.3

µA/

MHz

CoreMark

1.10

0.72

0.66

45.8

30.0

27.5

SecureMark

1.25

0.85

0.77

52.1

35.2

32.1

Dhrystone 2.1

1.15

0.75

0.69

47.9

31.0

28.8

Fibonacci

0.97

0.65

0.58

40.4

26.9

24.2

while(1)

0.89

0.61

0.55

36.9

25.2

22.7

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I

DD

(Run)

Supply 
current in 
Run mode

f

HCLK

 = f

PLL

 = 160 MHz,

PLL on HSE 16 MHz in bypass 
mode,
all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 1

Reduced Code

10.50

7.15

6.70

mA

65.6

44.7

41.9

µA/

MHz

CoreMark

10.50

7.05

6.55

65.6

44.1

40.9

SecureMark

11.50

7.85

7.35

71.9

49.1

45.9

Dhrystone 2.1

11.00

7.40

6.90

68.8

46.3

43.1

Fibonacci

8.25

5.65

5.30

51.6

35.3

33.1

while(1)

7.90

5.45

5.10

49.4

34.1

31.9

f

HCLK

 = f

PLL

 = 110 MHz,

PLL on HSE 16 MHz in bypass 
mode,
all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 2

Reduced Code

6.40

4.40

4.15

58.2

40.0

37.7

CoreMark

6.25

4.30

4.05

56.8

39.1

36.8

SecureMark

7.00

4.80

4.50

63.6

43.6

40.9

Dhrystone 2.1

6.55

4.50

4.25

59.5

40.9

38.6

Fibonacci

5.00

3.50

3.30

45.5

31.8

30.0

while(1)

4.80

3.35

3.20

43.6

30.5

29.1

f

HCLK

 = f

HSE

 = 55 MHz,

all peripherals disabled,
Flash bank 2 in power down,
all SRAMs enabled

Range 3

Reduced Code

3.05

2.20

2.15

55.5

40.0

39.1

CoreMark

3.05

2.20

2.10

55.5

40.0

38.2

SecureMark

3.40

2.45

2.30

61.8

44.5

41.8

Dhrystone 2.1

3.20

2.30

2.20

58.2

41.8

40.0

Fibonacci

2.40

1.80

1.75

43.6

32.7

31.8

while(1)

2.30

1.70

1.65

41.8

30.9

30.0

1. The current consumption from SRAM is similar.

Table 43. Typical current consumption in Run mode on SMPS, with different codes

running from Flash memory, ICACHE ON (1-way), prefetch ON

(1)

 (continued)

Symbol

Parameter

Conditions

Typ

Unit

Typ

Unit

-

Voltage 

scaling

Code

1.8 V

3 V

3.3 V

1.8 V

3 V

3.3 V

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Table 44. Current consumption in Sleep mode on LDO, Flash memory in power down 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

-

Voltage 

scaling

f

HCLK

 

(MHz)

25°C

55°C

85°C 105°C 125°C 30°C

55°C

85°C 105°C 125°C

I

DD

(Sleep)

Supply 
current in 
Sleep 
mode

f

HCLK

 = f

MSI

,

all peripherals disabled

Range 4

24

0.61

0.94

1.95

3.50

6.50

1.20

2.10

5.00

9.70

19.00

mA

16

0.49

0.81

1.80

3.35

6.40

1.10

1.90

4.90

9.50

19.00

12

0.43

0.75

1.75

3.30

6.30

0.95

1.90

4.80

9.50

19.00

4

0.25

0.58

1.55

3.10

6.15

0.76

1.70

4.60

9.30

19.00

2

0.22

0.55

1.55

3.10

6.10

0.72

1.60

4.60

9.30

19.00

1

0.21

0.53

1.55

3.05

6.10

0.71

1.60

4.60

9.20

19.00

0.4

0.19

0.52

1.50

3.05

6.05

0.69

1.60

4.50

9.20

19.00

0.1

0.19

0.52

1.50

3.05

6.10

0.69

1.60

4.50

9.20

19.00

f

HCLK

 = PLL on HSE 16 MHz 

in bypass mode,
all peripherals disabled

Range 1

160

4.35

4.95

6.65

9.10

13.50

6.10

8.10

15.00 26.00 46.00

140

3.90

4.50

6.15

8.65

13.50

5.60

7.60

15.00 25.00 46.00

120

3.45

4.05

5.75

8.20

13.00

5.10

7.10

14.00 25.00 46.00

Range 2

110

3.25

3.75

5.20

7.35

11.50

4.50

6.00

12.00 20.00 35.00

72

2.15

2.65

4.05

6.15

10.00

3.30

4.80

9.90

18.00 34.00

64

2.00

2.50

3.90

6.00

9.95

3.20

4.70

9.80

18.00 33.00

f

HCLK

 = f

HSE

 bypass mode,

all peripherals disabled

Range 3

55

1.45

1.85

3.05

4.85

8.40

2.30

3.40

7.30

14.00 26.00

32

1.00

1.40

2.60

4.40

7.85

1.80

2.90

6.80

13.00 25.00

1. Evaluated by characterization. Not tested in production.

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Table 45. 

Current consumption in Sleep mode on SMPS, Flash memory in power down

 

Symbol

Parameter

Conditions

Typ at V

DD

 = 1.8 V

Max at 1.71 V 

 V

DD

 

 3.6 V

(1)

 

(2)

Unit

-

Voltage 

scaling

f

HCLK

 

(MHz)

25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

I

DD

(Sleep)

Supply 
current in 
Sleep mode

f

HCLK

 = f

MSI

,

all peripherals disabled

Range 4

24

0.41

0.63

1.25

2.25

4.40

0.73

1.40

3.60

6.80

14.00

mA

16

0.27

0.53

1.20

2.20

4.30

0.57

1.30

3.50

6.70

14.00

12

0.24

0.48

1.15

2.20

4.25

0.53

1.20

3.50

6.70

14.00

4

0.14

0.34

1.05

2.05

4.10

0.42

1.10

3.40

6.50

13.00

2

0.12

0.34

1.05

2.05

4.10

0.39

1.00

3.40

6.50

13.00

1

0.11

0.33

1.05

2.05

4.10

0.38

0.99

3.40

6.50

13.00

0.4

0.10

0.31

1.05

2.05

4.10

0.38

0.97

3.40

6.50

13.00

0.1

0.10

0.31

1.05

2.05

4.10

0.37

0.97

3.40

6.50

13.00

f

HCLK

 = PLL on HSE 16 MHz 

in bypass mode,
all peripherals disabled

Range 1

160

3.50

3.95

5.20

7.00

10.50

4.80

6.20 12.00 19.00

34.00

140

3.10

3.60

4.80

6.60

10.00

4.30

5.80 12.00 19.00

34.00

120

2.80

3.25

4.50

6.30

9.70

4.00

5.40 11.00 19.00

33.00

Range 2

110

2.60

3.00

4.10

5.75

8.65

3.50

4.70

8.80

15.00

26.00

72

1.65

2.00

2.90

4.30

7.00

2.40

3.50

7.40

13.00

24.00

64

1.55

1.90

2.80

4.20

6.90

2.30

3.40

7.30

13.00

24.00

f

HCLK

 = f

HSE

 bypass mode,

all peripherals disabled

Range 3

55

1.10

1.40

2.25

3.55

5.90

1.70

2.50

5.60

9.80

19.00

32

0.85

1.10

1.90

3.15

5.60

1.40

2.20

5.10

9.40

18.00

1. Evaluated by characterization. Not tested in production.

2. The maximum value is at V

DD

 = 1.71 V in Sleep mode on SMPS.

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Table 46. 

Current consumption in Sleep mode on SMPS, 

Flash memory in power down,

 V

DD

 = 3.0 V

 

 

Symbol

Parameter

Conditions

Typ at V

DD

 = 3.0 V

Max at V

DD

 = 3.0 V

(1)

Unit

-

Voltage 

scaling

f

HCLK

 

(MHz)

25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

I

DD

(Sleep)

Supply 
current in 
Sleep mode

f

HCLK

 = f

MSI

,

all peripherals disabled

Range 4

24

0.26

0.40

0.83

1.50

2.80

0.66

1.20

2.20

4.20

8.20

mA

16

0.20

0.33

0.77

1.40

2.80

0.54

0.99

2.10

4.10

8.20

12

0.17

0.31

0.75

1.40

2.75

0.49

0.92

2.10

4.10

8.10

4

0.10

0.24

0.66

1.30

2.70

0.30

0.71

2.00

3.90

8.10

2

0.08

0.22

0.66

1.30

2.65

0.27

0.68

2.00

3.90

8.00

1

0.08

0.22

0.66

1.30

2.65

0.26

0.67

2.00

3.90

8.00

0.4

0.07

0.21

0.65

1.30

2.65

0.26

0.64

2.00

3.90

8.00

0.1

0.07

0.21

0.65

1.30

2.65

0.26

0.65

2.00

3.90

8.00

f

HCLK

 = PLL on HSE 16 MHz 

in bypass mode,
all peripherals disabled

Range 1

160

2.50

2.85

3.75

5.05

7.40

4.50

5.00

7.40

13.00

22.00

140

2.25

2.60

3.50

4.75

7.15

4.00

4.60

7.20

12.00

22.00

120

2.05

2.40

3.25

4.55

6.90

3.60

4.20

6.90

12.00

21.00

Range 2

110

1.95

2.25

3.00

4.10

6.05

3.20

3.60

5.70

9.30

17.00

72

1.30

1.55

2.20

3.20

5.10

2.20

2.60

4.80

8.30

16.00

64

1.20

1.45

2.15

3.15

5.00

2.00

2.50

4.70

8.20

16.00

f

HCLK

 = f

HSE

 bypass mode,

all peripherals disabled

Range 3

55

0.92

1.10

1.70

2.55

4.15

1.40

1.90

3.60

6.30

12.00

32

0.70

0.89

1.45

2.30

3.95

1.10

1.60

3.30

6.00

12.00

1. Evaluated by characterization. Not tested in production.

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Table 47. SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and SMPS 

Symbol

Parameter

Conditions

Typ

Max

Unit

-

Voltage 

scaling

f

HCLK

 

(MHz)

25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

I

DD

(SRAM1)

LDO

SRAM1 supply current in 
Run/Sleep mode (SRAM1PD = 1 
versus SRAM1PD = 0)

Range 4

24

0.02

0.05 0.16

0.33

0.68

0.06 0.15 0.48

1.00

2.05

mA

Range 1

160

0.04

0.10 0.28

0.55

1.07

0.15 0.30 0.83

1.65

3.20

Range 2

110

0.03

0.08 0.23

0.47

0.94

0.11

0.24 0.70

1.41

2.82

Range 3

55

0.02

0.06 0.19

0.40

0.81

0.08 0.19 0.58

1.20

2.43

I

DD

(SRAM3)

SRAM3 supply current in 
Run/Sleep mode (SRAM3PD = 1 
versus SRAM3PD = 0)

Range 4

24

0.04

0.13 0.41

0.87

1.78

0.15 0.39 1.24

2.62

5.34

Range 1

160

0.11

0.26 0.73

1.44

2.80

0.39 0.79 2.18

4.31

8.40

Range 2

110

0.08

0.21 0.60

1.22

2.44

0.28 0.62 1.81

3.67

7.32

Range 3

55

0.06

0.16 0.50

1.04

2.09

0.20 0.49 1.50

3.11

6.28

I

DD

(SRAM1)

SMPS,

V

DD

 = 3.0 V

SRAM1 supply current in 
Run/Sleep mode (SRAM1PD = 1 
versus SRAM1PD = 0)

Range 4

24

0.01

0.02 0.06

0.10

0.26

0.02 0.06 0.19

0.31

0.78

Range 1

160

0.02

0.05 0.14

0.28

0.55

0.07 0.15 0.43

0.84

1.64

Range 2

110

0.01

0.04 0.12

0.23

0.46

0.05 0.12 0.36

0.70

1.37

Range 3

55

0.01

0.03 0.09

0.18

0.36

0.04 0.09 0.27

0.55

1.09

I

DD

(SRAM3)

SRAM3 supply current in 
Run/Sleep mode (SRAM3PD = 1 
versus SRAM3PD = 0)

Range 4

24

0.02

0.05 0.17

0.32

0.69

0.06 0.16 0.51

0.95

2.07

Range 1

160

0.06

0.13 0.37

0.73

1.43

0.20 0.40 1.12

2.20

4.28

Range 2

100

0.04

0.10 0.30

0.61

1.19

0.14 0.31 0.91

1.84

3.57

Range 3

55

0.03

0.08 0.23

0.48

0.95

0.09 0.23 0.70

1.45

2.86

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I

DD

(SRAM1)

SMPS

(1)

SRAM1 supply current in 
Run/Sleep mode (SRAM1PD = 1 
versus SRAM1PD = 0)

Range 4

24

0.01

0.03

0.11

0.17

0.43

0.04

0.11

0.34

0.55

1.37

mA

Range 1

160

0.03

0.09 0.24

0.47

0.91

0.13 0.27 0.75

1.47

2.88

Range 2

110

0.02

0.07 0.20

0.39

0.76

0.09 0.21 0.63

1.23

2.41

Range 3

55

0.02

0.05 0.15

0.31

0.60

0.06 0.16 0.48

0.97

1.91

I

DD

(SRAM3)

SRAM3 supply current in 
Run/Sleep mode (SRAM3PD = 1 
versus SRAM3PD = 0)

Range 4

24

0.03

0.09 0.28

0.53

1.15

0.11

0.28 0.89

1.66

3.62

Range 1

160

0.09

0.22 0.62

1.22

2.38

0.35 0.71 1.96

3.87

7.52

Range 2

100

0.06

0.17 0.51

1.02

1.98

0.24 0.54 1.60

3.22

6.26

Range 3

55

0.04

0.13 0.39

0.80

1.59

0.16 0.40 1.24

2.54

5.01

1. The typical value is measured at V

DD

 = 1.8 V. The maximum value is for 1.71 V 

 V

DD

 

 3.6 V and is at V

DD

 = 1.71 V in Run/Sleep mode on SMPS.

Table 47. SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and SMPS (continued)

Symbol

Parameter

Conditions

Typ

Max

Unit

-

Voltage 

scaling

f

HCLK

 

(MHz)

25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

Table 48. Static power consumption of Flash banks, when supplied by LDO/SMPS 

Symbol

Parameter

Typ

Max

Unit

25°C

55°C

85°C 105°C 125°C

30°C

55°C

85°C 105°C 125°C

I

DD

(Flash_Bank1)

(1)

Flash bank 1 static consumption in normal mode
(PD1 = 1 versus PD1 = 0)

45.0

50.0

50.0

50.0

100.0

100.0 100.0 100.0

100.0

150.0

µA

I

DD

(Flash_Bank2)

(1)

Flash bank 2 static consumption in normal mode
(PD2 = 1 versus PD2 = 0)

45.0

50.0

50.0

50.0

100.0

100.0 100.0 100.0

100.0

150.0

I

DD

(Flash_Bank_LPM)

(2)

One Flash bank additional static consumption in 
normal mode versus low-power mode
(LPM = 0 versus LPM = 1)

25.0

25.0

25.0

25.0

50.0

40.0

40.0

40.0

40.0

70.0

1. When one bank is in power down, this consumption is saved. When Flash memory is in power down in Sleep mode (SLEEP_PD =1 ), Bank 1 and Bank 2 are in 

power down.

2. If no bank is in power-down, the Flash memory additional static consumption in normal mode versus low-power mode is 2 x I

DD(Flash_Bank_LPM)

.

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Table 49. 

Current consumption in Stop 0 mode on LDO

 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

I

DD(Stop 0)

Supply current in Stop 0 mode, 
regulator in Range 4, 
RTC disabled,
8-Kbyte SRAM2 + ICACHE 
retained

1.8

110

280

770

1500

3000

400

840

2400

4500

9000

µA

2.4

115

290

805

1600

3050

420

870

2500

4800

9200

3.0

115

295

820

1600

3150

420

890

2500

4800

9500

3.3

115

295

820

1600

3150

420

890

2500

4800

9500

3.6

115

295

825

1600

3150

420

890

2500

4800

9500

Supply current in Stop 0 mode, 
regulator in Range 4, 
RTC disabled,
All SRAMs retained

1.8

125

305

840

1650

3300

460

920

2600

5000

9900

2.4

125

315

875

1750

3400

460

950

2700

5300

11000

3.0

125

320

895

1800

3500

460

960

2700

5400

11000

3.3

130

320

890

1750

3500

470

960

2700

5300

11000

3.6

130

320

895

1800

3500

470

960

2700

5400

11000

1. Evaluated by characterization. Not tested in production.

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Table 50. 

Current consumption in Stop 0 mode on SMPS

 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

I

DD(Stop 0)

Supply current in Stop 0 mode, 
regulator in Range 4, 
RTC disabled,
8-Kbyte SRAM2 + ICACHE 
retained

1.8

54.5

160

535

1050

2100

200

480

1700

3200

6300

µA

2.4

38.5

115

360

890

1650

140

350

1100

2700

5000

3.0

39.5

115

340

685

1400

150

350

1100

2100

4200

3.3

37.0

105

315

640

1300

140

320

950

2000

3900

3.6

35.5

100

295

605

1200

130

300

890

1900

3600

Supply current in Stop 0 mode, 
regulator in Range 4, 
RTC disabled,
All SRAM retained

1.8

61.5

175

515

1200

2350

230

530

1600

3600

7100

2.4

43.5

125

400

930

1850

160

380

1200

2800

5600

3.0

44.5

125

370

770

1550

170

380

1200

2400

4700

3.3

41.5

115

345

705

1400

150

350

1100

2200

4200

3.6

40.0

110

325

665

1350

150

330

980

2000

4100

1. Evaluated by characterization. Not tested in production.

Table 51. Current consumption in Stop 1 mode on LDO 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

I

DD (Stop 1)

Supply current in Stop 1 mode, 
RTC disabled, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

82.0

250

755

1500

3000

300

750

2300

4500

9000

µA

2.4

83.5

250

750

1500

3050

310

750

2300

4500

9200

3.0

87.5

255

755

1550

3050

320

770

2300

4700

9200

3.3

84.0

250

755

1550

3050

310

750

2300

4700

9200

3.6

95.5

255

760

1550

3050

350

770

2300

4700

9200

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I

DD (Stop 1)

Supply current in Stop 1 mode, 
RTC disabled, 
All SRAMs retained

1.8

89.0

255

760

1550

3100

330

770

2300

4700

9300

µA

2.4

94.0

265

795

1600

3200

340

800

2400

4800

9600

3.0

100.0

270

815

1650

3300

370

810

2500

5000

9900

3.3

100.0

275

815

1650

3300

370

830

2500

5000

9900

3.6

110.0

275

825

1650

3300

400

830

2500

5000

9900

I

DD(Stop 1 

with RTC)

Supply current in Stop 1 mode, 
RTC

(2)

 clocked by LSI 32 kHz,

8-Kbyte SRAM2 + ICACHE 
retained

1.8

85.0

250

755

1500

3000

- -

-

-

-

2.4

88.5

250

750

1500

3050

- -

-

-

-

3.0

93.0

255

755

1550

3050

- -

-

-

-

3.3

89.0

250

755

1550

3050

- -

-

-

-

3.6

98.0

255

760

1550

3050

- -

-

-

-

Supply current in Stop 1 mode, 
RTC

(2) 

clocked by LSE 

bypassed at 32768 Hz, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

82.5

250

755

1500

3000

- -

-

-

-

2.4

84.0

250

750

1500

3050

- -

-

-

-

3.0

90.5

255

755

1550

3050

- -

-

-

-

3.3

84.5

250

755

1550

3050

- -

-

-

-

3.6

96.0

255

760

1550

3050

- -

-

-

-

Supply current in Stop 1 mode, 
RTC

(2)

 clocked by LSE quartz in 

low-drive mode,
LSESYSEN = 0 in RCC_BDCR, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

83.5

250

755

1500

3000

-

-

-

-

-

2.4

84.0

250

750

1500

3050

-

-

-

-

-

3.0

88.0

255

755

1550

3050

-

-

-

-

-

3.3

84.5

250

755

1550

3050

-

-

-

-

-

3.6

96.0

255

760

1550

3050

-

-

-

-

-

1. Evaluated by characterization. Not tested in production.

2. RTC with default configuration but LPCAL = 1 in RTC_CALR.

Table 51. Current consumption in Stop 1 mode on LDO (continued)

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

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Table 52. 

Current consumption during wake-up from Stop 1 mode on LDO

 

Symbol

Parameter

Conditions

Typ

Unit

-

V

DD

 (V)

25°C

Q

DD(wake-up from Stop 1)

Electrical charge consumed during wake-up from 
Stop 1 mode

Wake-up clock is MSI 24 MHz

3.0

40

nAs

Wake-up clock is HSI 16 MHz

40

Wake-up clock is MSI 1 MHz

70

Table 53. 

Current consumption in Stop 1 mode on SMPS

 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

I

DD(Stop 1)

Supply current in Stop 1 mode, 
RTC disabled, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

54.5

160

535

1050

2100

200

480

1700

3200

6300

µA

2.4

38.5

115

350

890

1650

140

350

1100

2700

5000

3.0

39.5

115

340

685

1400

150

350

1100

2100

4200

3.3

37.0

105

315

640

1300

140

320

950

2000

3900

3.6

35.5

100

295

600

1200

130

300

890

1800

3600

Supply current in Stop 1 mode, 
RTC disabled, 
All SRAMs retained

1.8

61.5

175

515

1200

2350

230

530

1600

3600

7100

2.4

43.5

125

390

930

1850

160

380

1200

2800

5600

3.0

44.0

125

370

770

1550

160

380

1200

2400

4700

3.3

41.5

115

345

705

1400

150

350

1100

2200

4200

3.6

39.5

110

325

665

1350

150

330

980

2000

4100

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DD(Stop 1 

with RTC)

Supply current in Stop 1 mode, 
RTC

(2)

 clocked by LSI 32 kHz,

8-Kbyte SRAM2 + ICACHE 
retained

1.8

54.5

160

535

1050

2100

-

-

-

-

-

µA

2.4

39.0

115

350

890

1650

-

-

-

-

-

3.0

40.0

115

340

685

1400

-

-

-

-

-

3.3

37.5

110

315

640

1300

-

-

-

-

-

3.6

36.0

100

295

600

1200

-

-

-

-

-

Supply current in Stop 1 mode, 
RTC

(2)

 clocked by LSE 

bypassed at 32768 Hz, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

65.0

180

535

890

2100

-

-

-

-

-

2.4

50.0

140

415

850

1700

-

-

-

-

-

3.0

42.0

120

345

705

1300

-

-

-

-

-

3.3

39.0

110

320

655

1250

-

-

-

-

-

3.6

38.0

105

300

620

1200

-

-

-

-

-

Supply current in Stop 1 mode, 
RTC

(2)

 clocked by LSE quartz 

in low-drive mode, 
LSESYSEN = 0 in RCC_BDCR, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

55.0

160

610

1050

2100

- -

-

-

-

2.4

39.5

150

490

890

1650

- -

-

-

-

3.0

39.5

115

340

685

1400

- -

-

-

-

3.3

37.0

105

315

640

1300

- -

-

-

-

3.6

35.5

100

295

600

1200

- -

-

-

-

1. Evaluated by characterization. Not tested in production.

2. RTC with default configuration but LPCAL = 1 in RTC_CALR.

Table 53. 

Current consumption in Stop 1 mode on SMPS

 (continued)

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

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Table 54. Current consumption during wake-up from Stop 1 mode on SMPS 

Symbol

Parameter

Conditions

Typ

Unit

-

V

DD

 (V)

25°C

Q

DD(wake-up from Stop 1)

Electrical charge consumed during wake-up from 
Stop 1 mode

Wake-up clock is MSI 24 MHz

3.0

40

nAs

Wake-up clock is HSI 16 MHz

40

Wake-up clock is MSI 1 MHz

70

Table 55. 

Current consumption in Stop 2 mode on LDO

 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

I

DD(Stop 2)

Supply current in Stop 2 mode, 
RTC disabled, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

8.90

23.5

70.0

145

305

33.0

71.0

210.0

440.0

920.0

µA

2.4

8.90

23.5

70.5

145

310

33.0

71.0

220.0

440.0

930.0

3.0

9.05

24.0

71.5

150

315

33.0

72.0

220.0

450.0

950.0

3.3

9.30

24.5

73.0

150

320

34.0

74.0

220.0

450.0

960.0

3.6

10.00

26.0

75.5

155

325

37.0

78.0

230.0

470.0

980.0

Supply current in Stop 2 mode, 
RTC disabled, 
All SRAMs retained

1.8

20.00

48.5

145.0

310

680

73.0

150.0

440.0

930.0

2100.0

2.4

20.00

48.5

145.0

315

680

73.0

150.0

440.0

950.0

2100.0

3.0

20.50

48.5

145.0

315

685

74.0

150.0

440.0

950.0

2100.0

3.3

20.50

49.5

150.0

315

690

74.0

150.0

450.0

950.0

2100.0

3.6

22.00

51.0

150.0

320

700

80.0

160.0

450.0

960.0

2100.0

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I

DD(Stop 2 

with RTC)

Supply current in Stop 2 mode, 
RTC

(2)

 clocked by LSI 32 kHz, 

8-Kbyte SRAM2 + ICACHE 
retained

1.8

9.45

24.0

71.5

150

315

35.0

72.0

220.0

450.0

950.0

µA

2.4

9.50

24.0

71.5

150

315

35.0

72.0

220.0

450.0

950.0

3.0

9.60

24.5

73.0

150

320

35.0

74.0

220.0

450.0

960.0

3.3

9.30

25.0

74.0

155

325

34.0

75.0

230.0

470.0

980.0

3.6

11.00

26.5

77.0

160

335

40.0

80.0

240.0

480.0

1100.0

Supply current in Stop 2 mode, 
RTC

(2)

 clocked by LSI 250 Hz, 

8-Kbyte SRAM2 + ICACHE 
retained

1.8

9.15

23.5

70.0

145

305

33.0

71.0

210.0

440.0

920.0

2.4

9.20

23.5

70.5

145

310

34.0

71.0

220.0

440.0

930.0

3.0

9.20

24.0

71.5

150

315

34.0

72.0

220.0

450.0

950.0

3.3

9.50

24.5

73.0

150

320

35.0

74.0

220.0

450.0

960.0

3.6

10.50

26.0

76.0

155

325

38.0

78.0

230.0

470.0

980.0

Supply current in Stop 2 mode, 
RTC

(2)

 clocked by LSE 

bypassed at 32768 Hz, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

9.15

24.0

71.5

150

315

33.0

72.0

220.0

450.0

950.0

2.4

9.20

24.0

71.5

150

315

34.0

72.0

220.0

450.0

950.0

3.0

9.50

24.0

72.5

150

320

35.0

72.0

220.0

450.0

960.0

3.3

9.50

25.0

74.0

155

325

35.0

75.0

230.0

470.0

980.0

3.6

10.50

26.5

76.5

160

335

38.0

80.0

230.0

480.0

1100.0

Supply current in Stop 2 mode, 
RTC

(2)

 clocked by LSE quartz in 

low-drive mode, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

9.45

23.5

70.5

145

305

-

-

-

-

-

2.4

9.50

24.0

71.0

150

310

-

-

-

-

-

3.0

9.35

24.0

72.0

150

315

-

-

-

-

-

3.3

9.75

25.0

73.5

150

320

-

-

-

-

-

3.6

10.60

26.5

76.0

155

325

-

-

-

-

-

1. Evaluated by characterization. Not tested in production.

2. RTC with default configuration but LPCAL = 1 in RTC_CALR.

Table 55. 

Current consumption in Stop 2 mode on LDO

 (continued)

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

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Table 56. 

SRAM static power consumption in Stop 2 when supplied by LDO

 

Symbol

Parameter

Typ

Max

(1)

Unit

25°C

55°C

85°C 105°C 125°C 30°C

55°C

85°C 105°C 125°C

I

DD(SRAM1_64kB)

(2)

SRAM1 64-Kbyte page x static consumption 
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)

0.8

2.0

6.0

13.2

28.6

3.0

6.0

18.0

40.0

86.0

µA

I

DD(SRAM2_8KB)

(3)

SRAM2 8-Kbyte page 1 static consumption 
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)

0.2

0.4

1.4

3.1

6.5

0.7

1.4

4.4

10.0

20.0

I

DD(SRAM2_56KB)

(3)

SRAM2 56-Kbyte page 2 static consumption 
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)

1.0

2.6

8.0

17.6

37.9

3.6

7.7

25.0

53.0

120.0

I

DD(SRAM3_64kB)

(4)

SRAM3 64-Kbyte page x static consumption 
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)

0.8

1.9

5.7

12.6

27.5

3.0

5.8

18.0

38.0

83.0

I

DD(SRAM4)

SRAM4 static consumption 
(SRAM4PDS = 1 versus SRAM4PDS = 0)

0.3

0.6

1.8

3.9

8.2

1.0

1.8

5.4

12.0

25.0

I

DD(ICRAM)

ICACHE SRAM static consumption 
(ICRAMPDS = 1 versus ICRAMPDS = 0)

0.1

0.4

1.3

2.9

5.7

0.5

1.3

4.0

8.6

18.0

I

DD(DC1RAM)

DCACHE1 SRAM static consumption 
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)

0.1

0.2

0.7

1.5

3.0

0.3

0.7

2.3

4.6

9.1

I

DD(DMA2DRAM)

DMA2D SRAM static consumption 
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)

0.0

0.1

0.3

0.5

0.7

0.2

0.3

1.0

1.6

2.0

I

DD(PRAM)

FMAC, FDCAN and USB SRAM static consumption 
(PRAMPDS = 1 versus PRAMPDS = 0)

0.0

0.1

0.4

0.7

1.1

0.2

0.4

1.3

2.3

3.2

1. Evaluated by characterization. Not tested in production.

2. SRAM1 total consumption is 3 × I

DD(SRAM1_64KB)

.

3. SRAM2 total consumption is I

DD(SRAM2_8KB)

 + I

DD(SRAM2_56KB)

.

4. SRAM3 total consumption is 8 × I

DD(SRAM3_64KB)

.

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Table 57. 

Current consumption during wake-up from Stop 2 mode on LDO

 

Symbol

Parameter

Conditions

Typ

Unit

-

V

DD

 (V)

25°C

Q

DD(wake-up from Stop 2)

Electrical charge consumed during wake-up from 
Stop 2 mode

Wake-up clock is MSI 24 MHz

3.0

30

nAs

Wake-up clock is HSI 16 MHz

30

Wake-up clock is MSI 1 MHz

70

Table 58. 

Current consumption in Stop 2 mode on SMPS

 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

I

DD(Stop 2)

Supply current in Stop 2 mode, 
RTC disabled, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

5.30

14.0

42.0

88.5

195

19.0

42.0

130.0

270.0

580.0

µA

2.4

3.50

9.6

29.5

63.5

140

13.0

29.0

87.0

190.0

410.0

3.0

3.90

10.0

31.5

68.0

150

14.0

30.0

93.0

200.0

440.0

3.3

3.90

10.0

30.5

65.5

145

14.0

30.0

89.0

190.0

420.0

3.6

4.55

11.0

31.0

65.0

145

16.0

32.0

89.0

190.0

420.0

Supply current in Stop 2 mode, 
RTC disabled, 
ALL SRAMs retained

1.8

12.00

28.5

83.5

180.0

440

44.0

86.0

250.0

540.0

1400.0

2.4

7.85

19.5

58.5

125.0

280

29.0

59.0

180.0

380.0

830.0

3.0

8.55

20.5

61.0

130.0

290

31.0

61.0

190.0

390.0

860.0

3.3

8.20

19.5

57.5

125.0

275

30.0

58.0

170.0

370.0

810.0

3.6

8.55

19.5

56.0

120.0

265

30.0

57.0

170.0

360.0

780.0

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I

DD(Stop 2 

with RTC)

Supply current in Stop 2 mode, 
RTC

(2)

 clocked by LSI 32 kHz, 

8-Kbyte SRAM2 + ICACHE 
retained

1.8

5.60

14.0

42.0

89.0

195

20.0

42.0

130.0

270.0

580.0

µA

2.4

3.85

10.0

30.0

63.5

140

14.0

30.0

89.0

190.0

410.0

3.0

4.35

10.5

32.0

68.5

150

16.0

31.0

94.0

200.0

440.0

3.3

4.40

10.5

31.0

66.0

145

16.0

31.0

91.0

200.0

420.0

3.6

5.15

11.5

31.5

66.0

145

18.0

33.0

91.0

190.0

420.0

Supply current in Stop 2 mode, 
RTC

(2)

 clocked by LSI 250 Hz, 

8-Kbyte SRAM2 + ICACHE 
retained

1.8

5.40

14.0

42.0

89.0

195

20.0

42.0

130.0

270.0

580.0

2.4

3.60

9.8

30.0

63.5

140

13.0

29.0

89.0

190.0

410.0

3.0

4.00

10.5

31.5

68.0

150

15.0

31.0

93.0

200.0

440.0

3.3

4.05

10.5

31.0

65.5

145

15.0

31.0

91.0

190.0

420.0

3.6

4.75

11.0

31.5

65.5

145

17.0

32.0

91.0

190.0

420.0

Supply current in Stop 2 mode, 
RTC

(2)

 clocked by LSE 

bypassed at 32768 Hz, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

5.50

14.0

42.0

89.0

195

20.0

42.0

130.0

270.0

580.0

2.4

3.70

9.9

30.0

63.5

140

14.0

30.0

89.0

190.0

410.0

3.0

4.15

10.5

32.0

68.0

150

15.0

31.0

94.0

200.0

440.0

3.3

4.20

10.5

31.0

66.0

145

15.0

31.0

91.0

200.0

420.0

3.6

4.90

11.0

31.5

65.5

145

17.0

32.0

91.0

190.0

420.0

Supply current in Stop 2 mode, 
RTC

(2)

 clocked by LSE quartz in 

low-drive mode,
8-Kbyte SRAM2 + ICACHE 
retained

1.8

5.60

14.0

42.0

88.5

195

-

-

-

-

-

2.4

3.90

9.9

30.0

63.5

140

-

-

-

-

-

3.0

4.25

10.5

31.5

68.0

150

-

-

-

-

-

3.3

4.30

10.5

31.0

65.5

145

-

-

-

-

-

3.6

4.95

11.0

31.5

65.0

145

-

-

-

-

-

1. Evaluated by characterization. Not tested in production.

2. RTC with default configuration but LPCAL = 1 in RTC_CALR.

Table 58. 

Current consumption in Stop 2 mode on SMPS

 (continued)

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

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Table 59. SRAM static power consumption in Stop 2 when supplied by SMPS 

Symbol

Parameter

Typ

Max

(1)

Unit

25°C

55°C

85°C 105°C 125°C 30°C

55°C

85°C 105°C 125°C

I

DD(SRAM1_64kB)

(2)

SRAM1 64-Kbyte page x static consumption 
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)

0.4

0.9

2.6

5.5

12.7

1.5

2.7

7.7

17.0

39.0

µA

I

DD(SRAM2_8KB)

(3)

SRAM2 8-Kbyte page 1 static consumption 
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)

0.1

0.2

0.6

1.2

2.9

0.3

0.6

2.0

3.7

10.0

I

DD(SRAM2_56KB)

(3)

SRAM2 56-Kbyte page 2 static consumption 
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)

0.5

1.1

3.4

7.5

16.7

1.7

3.4

11.0

23.0

50.0

I

DD(SRAM3_64kB)

(4)

SRAM3 64-Kbyte page x static consumption 
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)

0.4

0.8

2.4

5.3

12.2

1.4

2.5

7.3

16.0

37.0

I

DD(SRAM4)

SRAM4 static consumption 
(SRAM4PDS = 1 versus SRAM4PDS = 0)

0.1

0.3

0.7

1.5

3.7

0.4

0.8

2.2

4.6

12.0

I

DD(ICRAM)

ICACHE SRAM static consumption 
(ICRAMPDS = 1 versus ICRAMPDS = 0)

0.1

0.2

0.5

1.0

2.6

0.3

0.5

2.0

3.1

7.9

I

DD(DC1RAM)

DCACHE1 SRAM static consumption 
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)

0.0

0.1

0.3

0.4

1.3

0.2

0.3

1.0

1.4

4.0

I

DD(DMA2DRAM)

DMA2D SRAM static consumption 
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)

0.0

0.0

0.1

0.2

0.4

0.1

0.1

0.2

0.6

1.1

I

DD(PRAM)

FMAC, FDCAN and USB SRAM static consumption
(PRAMPDS = 1 versus PRAMPDS = 0)

0.0

0.0

0.1

0.2

0.6

0.1

0.1

0.3

0.6

1.8

1. Evaluated by characterization. Not tested in production.

2. SRAM1 total consumption is 3 × I

DD(SRAM1_64KB)

.

3. SRAM2 total consumption is I

DD(SRAM2_8KB)

 + I

DD(SRAM2_56KB)

.

4. SRAM3 total consumption is 8 × I

DD(SRAM3_64KB)

.

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Table 60. Current consumption during wake-up from Stop 2 mode on SMPS 

Symbol

Parameter

Conditions

Typ

Unit

-

V

DD

 (V)

25°C

Q

DD(wake-up from Stop 2)

Electrical charge consumed during wake-up from 
Stop 2 mode

Wake-up clock is MSI 24 MHz

3.0

30

nAs

Wake-up clock is HSI 16 MHz

30

Wake-up clock is MSI 1 MHz

70

Table 61. 

Current consumption in Stop 3 mode on LDO

 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

I

DD(Stop 3)

Supply current in Stop 3 mode, 
RTC disabled,
8-Kbyte SRAM2 + ICACHE 
retained

1.8

5.15

14.5

49.0

110

240

19.0

44.0

150.0

330.0

710.0

µA

2.4

5.15

15.0

49.5

110

240

19.0

45.0

150.0

330.0

710.0

3.0

5.60

15.0

50.5

110

245

20.0

45.0

150.0

330.0

720.0

3.3

5.30

15.5

51.5

115

250

19.0

46.0

160.0

340.0

740.0

3.6

6.80

17.0

54.0

115

255

24.0

50.0

160.0

340.0

750.0

Supply current in Stop 3 mode, 
RTC disabled,
all SRAMs retained

1.8

12.00

35.5

125.0

290

665

44.0

110.0

380.0

870.0

2000.0

2.4

12.00

36.0

125.0

295

670

44.0

110.0

380.0

890.0

2000.0

3.0

13.00

36.5

130.0

300

675

47.0

110.0

390.0

900.0

2100.0

3.3

14.50

37.0

130.0

300

685

52.0

120.0

390.0

900.0

2100.0

3.6

14.50

39.0

135.0

305

695

52.0

120.0

410.0

910.0

2100.0

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I

DD(Stop 3 

with RTC)

Supply current in Stop 3 mode, 
RTC

(2)

 clocked by LSI 32 kHz, 

8-Kbyte SRAM2 + ICACHE 
retained

1.8

5.45

15.0

49.5

110

240

20.0

45.0

150.0

330.0

710.0

µA

2.4

5.55

15.0

50.0

110

240

20.0

45.0

150.0

330.0

710.0

3.0

6.05

15.5

51.0

110

245

22.0

46.0

160.0

330.0

720.0

3.3

5.80

16.0

52.0

115

250

21.0

48.0

160.0

340.0

740.0

3.6

7.35

18.0

54.5

120

255

26.0

53.0

160.0

360.0

750.0

Supply current in Stop 3 mode, 
RTC

(2)

 clocked by LSI 250 Hz, 

8-Kbyte SRAM2 + ICACHE 
retained

1.8

5.25

15.0

49.5

110

240

19.0

45.0

150.0

330.0

710.0

2.4

5.30

15.0

49.5

110

240

19.0

45.0

150.0

330.0

710.0

3.0

5.75

15.0

50.5

110

245

21.0

45.0

150.0

330.0

720.0

3.3

5.40

16.0

52.0

115

250

19.0

48.0

160.0

340.0

740.0

3.6

6.95

17.5

54.5

115

255

25.0

51.0

160.0

340.0

750.0

Supply current in Stop 3 mode, 
RTC

(2)

 clocked by LSE 

bypassed at 32768 Hz, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

5.35

15.0

49.5

110

240

20.0

45.0

150.0

330.0

710.0

2.4

5.40

15.0

49.5

110

240

20.0

45.0

150.0

330.0

710.0

3.0

5.90

15.5

50.5

110

245

21.0

46.0

150.0

330.0

720.0

3.3

5.55

16.0

52.0

115

250

20.0

48.0

160.0

340.0

740.0

3.6

7.20

17.5

54.5

115

255

25.0

51.0

160.0

340.0

750.0

Supply current in Stop 3 mode, 
RTC

(2)

 clocked by LSE quartz in 

low-drive mode, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

5.45

15.0

49.0

110

240

-

-

-

-

-

2.4

5.55

15.0

49.5

110

240

-

-

-

-

-

3.0

6.05

15.5

50.5

110

245

-

-

-

-

-

3.3

6.65

16.0

51.5

115

250

-

-

-

-

-

3.6

7.30

17.5

54.0

115

255

-

-

-

-

-

1. Evaluated by characterization. Not tested in production.

2. RTC with default configuration but LPCAL = 1 in RTC_CALR.

Table 61. 

Current consumption in Stop 3 mode on LDO

 (continued)

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

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Table 62. SRAM static power consumption in Stop 3 when supplied by LDO 

Symbol

Parameter

Typ

Max

(1)

Unit

25°C

55°C

85°C 105°C 125°C 30°C

55°C

85°C 105°C 125°C

I

DD(SRAM1_64kB)

(2)

SRAM1 64-Kbyte page x static consumption 
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)

0.7

1.8

6.4

15.3

35.6

2.7

5.3

20.0

46.0

110.0

µA

I

DD(SRAM2_8KB)

(3)

SRAM2 8-Kbyte page 1 static consumption 
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)

0.2

0.7

2.4

5.8

12.8

1.0

2.1

7.1

18.0

39.0

I

DD(SRAM2_56KB)

(3)

SRAM2 56-Kbyte page 2 static consumption 
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)

0.9

2.2

7.8

18.5

41.7

3.2

6.5

24.0

56.0

130.0

I

DD(SRAM3_64kB)

(4)

SRAM3 64-Kbyte page x static consumption 
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)

0.7

1.7

6.1

14.8

34.2

2.6

5.2

19.0

45.0

110.0

I

DD(SRAM4)

SRAM4 static consumption 
(SRAM4PDS = 1 versus SRAM4PDS = 0)

0.2

0.5

1.7

4.0

8.9

0.8

1.5

5.1

12.0

27.0

I

DD(ICRAM)

ICACHE SRAM static consumption 
(ICRAMPDS = 1 versus ICRAMPDS = 0)

0.0

0.3

1.3

2.9

6.3

0.0

1.1

3.9

8.9

19.0

I

DD(DC1RAM)

DCACHE1 SRAM static consumption 
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)

0.0

0.0

0.0

0.3

1.2

0.0

0.0

0.0

1.0

3.7

I

DD(DMA2DRAM)

DMA2D SRAM static consumption 
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)

0.0

0.1

0.3

0.6

1.1

0.2

0.2

1.0

1.9

3.4

I

DD(PRAM)

FMAC, FDCAN and USB SRAM static consumption
(PRAMPDS = 1 versus PRAMPDS = 0)

0.1

0.1

0.4

0.8

1.5

0.2

0.3

1.3

2.3

4.6

1. Evaluated by characterization. Not tested in production.

2. SRAM1 total consumption is 3 × I

DD(SRAM1_64KB)

.

3. SRAM2 total consumption is I

DD(SRAM2_8KB)

 + I

DD(SRAM2_56KB)

.

4. SRAM3 total consumption is 8 × I

DD(SRAM3_64KB)

.

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Table 63. Current consumption during wake-up from Stop 3 mode on LDO 

Symbol

Parameter

Conditions

Typ

(1)

Unit

-

V

DD

 (V)

25°C

Q

DD(wake-up from Stop 3)

Electrical charge consumed during wake-up from 
Stop 3 mode

Wake-up clock is MSI 24 MHz

3.0

430

nAs

Wake-up clock is HSI 16 MHz

410

Wake-up clock is MSI 1 MHz

610

1. Evaluated by characterization in worse case condition (V

CAP

 = 0.7 V before wake-up).

Table 64. 

Current consumption in Stop 3 mode on SMPS

 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

I

DD(Stop 3)

Supply current in Stop 3 mode, 
RTC disabled,
8-Kbyte SRAM2 + ICACHE 
retained

1.8

2.10

6.55

22.5

50.5

115.0

7.4

20.0

66.0

150.0

340.0

µA

2.4

1.85

5.95

20.5

46.5

110.0

6.5

18.0

60.0

140.0

320.0

3.0

1.70

5.30

18.5

42.0

98.5

5.9

16.0

54.0

130.0

280.0

3.3

1.80

5.55

18.5

41.5

97.0

6.1

16.0

53.0

120.0

280.0

3.6

2.65

6.55

19.5

42.5

98.0

8.6

19.0

55.0

120.0

280.0

Supply current in Stop 3 mode, 
RTC disabled,
all SRAMs retained

1.8

5.20

15.50

55.0

130.0

355.0

19.0

47.0

170.0

390.0

1100.0

2.4

4.55

14.00

50.0

115.0

275.0

17.0

42.0

150.0

350.0

820.0

3.0

3.90

12.00

42.5

100.0

235.0

14.0

36.0

130.0

300.0

690.0

3.3

3.65

11.50

40.5

95.0

225.0

13.0

34.0

120.0

280.0

660.0

3.6

4.50

12.00

40.5

92.5

215.0

16.0

35.0

120.0

270.0

630.0

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DD(Stop 3 

with RTC)

Supply current in Stop 3 mode, 
RTC

(2)

 clocked by LSI 32 kHz, 

8-Kbyte SRAM2 + ICACHE 
retained

1.8

2.40

6.85

22.5

51.0

120.0

8.5

21.0

66.0

150.0

350.0

µA

2.4

2.25

6.30

21.0

47.0

110.0

8.0

19.0

62.0

140.0

320.0

3.0

2.15

5.80

19.0

42.5

99.0

7.5

17.0

55.0

130.0

290.0

3.3

2.30

6.05

19.0

42.0

97.5

7.9

18.0

55.0

120.0

280.0

3.6

3.20

7.10

20.0

43.0

98.5

11.0

20.0

56.0

130.0

280.0

Supply current in Stop 3 mode, 
RTC

(2)

 clocked by LSI 250 Hz, 

8-Kbyte SRAM2 + ICACHE 
retained

1.8

2.20

6.70

22.5

50.5

115.0

7.8

20.0

66.0

150.0

340.0

2.4

2.00

6.10

20.5

47.0

110.0

7.1

18.0

60.0

140.0

320.0

3.0

1.85

5.45

18.5

42.0

98.5

6.5

16.0

54.0

130.0

280.0

3.3

1.90

5.70

18.5

41.5

97.0

6.4

17.0

53.0

120.0

280.0

3.6

2.80

6.70

20.0

42.5

98.0

9.2

19.0

56.0

120.0

280.0

Supply current in Stop 3 mode, 
RTC

(2)

 clocked by LSE bypassed 

at 32768 Hz, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

2.30

6.80

22.5

51.0

120.0

8.2

21.0

66.0

150.0

350.0

2.4

2.10

6.20

21.0

47.0

110.0

7.4

19.0

62.0

140.0

320.0

3.0

2.00

5.60

18.5

42.0

99.0

7.0

17.0

54.0

130.0

290.0

3.3

2.05

5.85

18.5

42.0

97.5

7.0

17.0

53.0

120.0

280.0

3.6

3.00

6.90

20.0

43.0

98.5

9.9

20.0

56.0

130.0

280.0

Supply current in Stop 3 mode, 
RTC

(2)

 clocked by LSE quartz in 

low-drive mode, 
8-Kbyte SRAM2 + ICACHE 
retained

1.8

2.45

6.90

22.5

50.5

115.0

-

-

-

-

-

2.4

2.25

6.35

21.0

46.5

110.0

-

-

-

-

-

3.0

2.15

5.80

18.5

42.0

98.5

-

-

-

-

-

3.3

2.35

6.05

18.5

41.5

97.0

-

-

-

-

-

3.6

3.15

7.05

20.0

42.5

98.0

-

-

-

-

-

1. Evaluated by characterization. Not tested in production.

2. RTC with default configuration but LPCAL = 1 in RTC_CALR.

Table 64. 

Current consumption in Stop 3 mode on SMPS

 (continued)

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

V

DD

 (V)

25°C

55°C

85°C

105°C

125°C

30°C

55°C

85°C

105°C

125°C

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Table 65. SRAM static power consumption in Stop 3 when supplied by SMPS 

Symbol

Parameter

Typ

Max

(1)

Unit

25°C

55°C

85°C 105°C 125°C 30°C

55°C

85°C 105°C 125°C

I

DD(SRAM1_64kB)

(2)

SRAM1 64-Kbyte page x static consumption 
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)

0.2

0.6

2.2

5.4

12.6

0.7

2.0

8.0

17.0

38.0

µA

I

DD(SRAM2_8KB)

(3)

SRAM2 8-Kbyte page 1 static consumption 
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)

0.1

0.2

0.8

2.0

4.6

0.2

1.0

2.5

5.9

14.0

I

DD(SRAM2_56KB)

(3)

SRAM2 56-Kbyte page 2 static consumption 
(SRAM2PDS2 = 1 versus SRAM2PDS2 = 0)

0.2

0.7

2.7

6.4

14.8

1.0

3.0

8.0

20.0

45.0

I

DD(SRAM3_64kB)

(4)

SRAM3 64-Kbyte page x static consumption 
(SRAM3PDSx = 1 versus SRAM3PDSx = 0)

0.2

0.6

2.1

5.0

12.0

1.0

2.0

6.3

16.0

36.0

I

DD(SRAM4)

SRAM4 static consumption 
(SRAM4PDS = 1 versus SRAM4PDS = 0)

0.0

0.1

0.6

1.4

3.0

0.5

1.0

2.0

4.1

8.9

I

DD(ICRAM)

ICACHE SRAM static consumption 
(ICRAMPDS = 1 versus ICRAMPDS = 0)

0.0

0.1

0.4

1.0

2.0

0.1

1.0

2.0

3.0

6.1

I

DD(DC1RAM)

DCACHE1 SRAM static consumption 
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)

0.0

0.1

0.2

0.5

0.9

1.2

1.0

1.0

1.5

2.6

I

DD(DMA2DRAM)

DMA2D SRAM static consumption 
(DMA2DRAMPDS = 1 versus DMA2DRAMPDS = 0)

0.0

0.0

0.0

0.1

0.1

0.4

0.1

0.1

0.4

0.4

I

DD(PRAM)

FMAC, FDCAN and USB SRAM static consumption 
(PRAMPDS = 1 versus PRAMPDS = 0)

0.0

0.0

0.1

0.2

0.3

0.0

0.1

1.0

0.7

0.8

1. Evaluated by characterization. Not tested in production.

2. SRAM1 total consumption is 3 × I

DD(SRAM1_64KB)

.

3. SRAM2 total consumption is I

DD(SRAM2_8KB)

 + I

DD(SRAM2_56KB)

.

4. SRAM3 total consumption is 8 × I

DD(SRAM3_64KB)

.

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Table 66. Current consumption during wake-up from Stop 3 mode on SMPS 

Symbol

Parameter

Conditions

Typ

(1)

Unit

-

V

DD

 (V)

25°C

Q

DD(wake-up from Stop 3)

Electrical charge consumed during wake-up from 
Stop 3 mode

Wake-up clock is MSI 24 MHz

3.0

160

nAs

Wake-up clock is HSI 16 MHz

150

Wake-up clock is MSI 1 MHz

250

1. Evaluated by characterization in worse case condition (V

DD11

 = 0.7 V before wake-up).

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Table 67. 

Current consumption in Standby mode

 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

-

V

DD

 (V)

25°C

55°C

85°C 105°C 125°C 30°C

55°C

85°C 105°C 125°C

I

DD(Standby)

Supply current in 
Standby mode (backup 
registers retained), 
RTC disabled

No IWDG
ULPMEN = 1

1.8

0.21

0.71

3.30

9.10

28.40

0.55

1.70

7.40

20.00

58.00

µA

2.4

0.21

0.74

3.47

9.54

29.70

0.58

1.80

7.90

22.00

61.00

3.0

0.36

1.08

4.41

11.50 34.20

1.10

2.70

11.00 27.00

73.00

3.3

0.64

1.69

5.68

13.70 38.40

2.00

4.20

14.00 32.00

83.00

3.6

1.51

3.04

8.07

17.40 44.20

4.80

7.70

20.00 41.00

98.00

No IWDG
ULPMEN = 0

1.8

0.28

0.76

3.28

8.95

27.70

0.63

1.70

7.40

20.00

57.00

2.4

0.29

0.83

3.52

9.46

29.10

0.67

1.90

7.90

22.00

61.00

3.0

0.43

1.16

4.43

11.40 33.40

1.10

2.80

11.00 27.00

72.00

3.3

0.75

1.75

5.68

13.60 37.40

2.20

4.30

14.00 32.00

82.00

3.6

1.58

3.10

8.07

17.20 43.30

4.90

7.70

20.00 41.00

97.00

with IWDG 
clocked by 
LSI 32 kHz
ULPMEN = 0

1.8

0.52

1.03

3.55

9.04

26.57

0.79

1.90

7.20

19.00

57.00

2.4

0.64

1.18

3.81

9.51

27.47

0.93

2.10

7.80

20.00

61.00

3.0

0.87

1.62

4.81

11.48 31.63

1.50

3.10

11.00 25.00

72.00

3.3

1.23

2.26

6.12

13.68 35.58

2.60

4.60

14.00 30.00

83.00

3.6

2.13

3.67

8.55

17.34 41.46

5.30

8.10

20.00 39.00

97.00

with IWDG 
clocked by 
LSI 250 Hz
ULPMEN = 0

1.8

0.38

0.88

3.44

9.15

28.00

0.77

1.90

7.60

21.00

57.00

2.4

0.40

0.94

3.63

9.58

29.20

0.79

2.00

8.00

22.00

61.00

3.0

0.55

1.28

4.55

11.50 33.50

1.30

2.90

11.00 27.00

72.00

3.3

0.87

1.90

5.83

13.70 37.50

2.30

4.40

14.00 32.00

82.00

3.6

1.71

3.26

8.22

17.30 43.30

5.10

7.90

20.00 41.00

97.00

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DD(Standby with 

RTC)

Supply current in 
Standby mode (backup 
registers retained), 
RTC enabled

RTC

(2)

 clocked 

by LSI 32 kHz,
no IWDG

(3)

ULPMEN = 0

1.8

0.56

1.05

3.60

9.29

28.10

0.81

1.90

7.50

20.00

57.00

µA

2.4

0.64

1.18

3.88

9.82

29.40

0.93

2.20

8.20

22.00

61.00

3.0

0.88

1.61

4.88

11.80 33.80

1.50

3.20

11.00 27.00

72.00

3.3

1.25

2.26

6.19

14.10 37.80

2.60

4.70

14.00 33.00

83.00

3.6

2.13

3.67

8.63

17.70 43.70

5.30

8.20

20.00 42.00

97.00

RTC

(2)

 clocked 

by LSI 250 Hz,
no IWDG
ULPMEN = 0

1.8

0.39

0.88

3.44

9.14

28.00

0.77

1.90

7.60

21.00

57.00

2.4

0.40

0.94

3.63

9.58

29.20

0.79

2.00

8.00

22.00

61.00

3.0

0.56

1.29

4.56

11.50 33.40

1.30

2.90

11.00 27.00

72.00

3.3

0.89

1.90

5.83

13.70 37.50

2.30

4.40

14.00 32.00

82.00

3.6

1.73

3.27

8.23

17.30 43.30

5.10

7.90

20.00 41.00

97.00

RTC

(2)

 clocked 

by LSE 
bypassed at 
32768 Hz
ULPMEN = 0

1.8

0.47

0.96

3.51

9.22

28.10

0.95

2.10

7.70

21.00

57.00

2.4

0.50

1.04

3.75

9.72

29.40

1.10

2.30

8.30

22.00

61.00

3.0

0.69

1.42

4.71

11.70 33.80

1.60

3.30

11.00 27.00

73.00

3.3

1.04

2.06

6.00

13.90 37.80

2.70

4.80

15.00 33.00

83.00

3.6

1.91

3.46

8.43

17.60 43.70

5.50

8.30

21.00 42.00

98.00

RTC

(2)

 clocked 

by LSE quartz 
in low-drive 
mode
ULPMEN = 0

1.8

0.56

1.07

3.61

9.25

27.30

-

-

-

-

-

2.4

0.59

1.15

3.83

9.70

28.30

-

-

-

-

-

3.0

0.75

1.50

4.77

11.60 32.60

-

-

-

-

-

3.3

1.07

2.11

6.04

13.80 36.60

-

-

-

-

-

3.6

1.91

3.47

8.43

17.50 42.40

-

-

-

-

-

Table 67. 

Current consumption in Standby mode

 (continued)

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

-

V

DD

 (V)

25°C

55°C

85°C 105°C 125°C 30°C

55°C

85°C 105°C 125°C

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I

DD(Standby with 

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Supply current in 
Standby mode (backup 
registers retained), 
RTC enabled

RTC

(2)

 clocked 

by LSE quartz 
in low-drive 
mode
ULPMEN = 1

1.8

0.53

1.07

3.65

9.55

29.30

-

-

-

-

-

µA

2.4

0.56

1.13

3.90

10.10 30.10

-

-

-

-

-

3.0

0.71

1.47

4.85

12.45 35.30

-

-

-

-

-

3.3

1.07

2.06

6.10

14.55 39.00

-

-

-

-

-

3.6

1.86

3.50

8.60

17.90 45.50

-

-

-

-

-

I

DD(BKPSRAM)

Supply current to be 
added in Standby mode 
when backup SRAM is 
retained

-

1.8

0.13

0.22

0.53

1.15

2.50

0.47

0.66

1.60

3.50

7.50

2.4

0.12

0.19

0.47

1.04

2.30

0.45

0.56

1.50

3.20

6.90

3.0

0.13

0.19

0.47

1.00

2.30

0.47

0.58

1.50

3.00

7.00

3.3

0.09

0.20

0.48

1.00

2.40

0.31

0.60

1.50

3.00

7.20

3.6

0.10

0.20

0.48

1.00

2.20

0.37

0.60

1.50

3.00

6.70

I

DD(SRAM2)

Supply current to be 
added in Standby mode 
when full SRAM2 and 
BKPSRAM are retained

LDO

1.8

1.62

4.09

11.92 25.75 55.60

5.90

13.00 36.00 78.00 170.00

2.4

1.62

4.05

11.88 25.74 55.60

5.90

13.00 36.00 78.00 170.00

3.0

1.64

4.02

11.87 25.80 55.70

6.00

13.00 36.00 78.00 170.00

3.3

1.65

4.02

11.82 25.70 55.70

6.00

13.00 36.00 78.00 170.00

3.6

1.68

3.99

11.73 25.50 55.20

6.10

12.00 36.00 77.00 170.00

I

DD(SRAM2_8K)

Supply current to be 
added in Standby mode 
when SRAM2 8-Kbyte 
page 1 and BKPSRAM 
are retained

1.8

0.58

1.41

4.02

8.55

18.20

2.10

4.30

13.00 26.00

55.00

2.4

0.63

1.37

3.95

8.44

17.90

2.30

4.10

12.00 26.00

54.00

3.0

0.63

1.36

3.93

8.40

17.90

2.30

4.10

12.00 26.00

54.00

3.3

0.60

1.35

3.90

8.30

17.80

2.20

4.10

12.00 25.00

54.00

3.6

0.69

1.35

3.73

8.10

17.30

2.50

4.10

12.00 25.00

52.00

Table 67. 

Current consumption in Standby mode

 (continued)

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

-

V

DD

 (V)

25°C

55°C

85°C 105°C 125°C 30°C

55°C

85°C 105°C 125°C

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I

DD(SRAM2)

Supply current to be 
added in Standby mode 
when full SRAM2 and 
BKPSRAM are retained

SMPS

1.8

0.97

2.23

6.55

14.25 31.40

3.50

6.70

20.00 43.00

95.00

µA

2.4

0.63

1.48

4.40

9.44

19.50

2.30

4.50

14.00 29.00

59.00

3.0

0.67

1.51

4.50

9.90

21.60

2.50

4.60

14.00 30.00

65.00

3.3

0.56

1.35

4.05

8.90

19.60

2.10

4.10

13.00 27.00

59.00

3.6

0.55

1.19

3.53

7.80

17.40

2.00

3.60

11.00 24.00

53.00

I

DD(SRAM2_8K)

Supply current to be 
added in Standby mode 
when SRAM2 8-Kbyte 
page 1 and BKPSRAM 
are retained

1.8

0.34

0.78

2.21

4.75

10.40

1.30

2.40

6.70

15.00

32.00

2.4

0.24

0.52

1.45

3.04

6.80

0.85

1.60

4.40

9.20

21.00

3.0

0.25

0.50

1.45

3.10

6.80

0.89

1.50

4.40

9.30

21.00

3.3

0.17

0.42

1.23

2.70

6.00

0.63

1.30

3.70

8.10

18.00

3.6

0.18

0.33

0.86

2.10

4.80

0.65

0.99

2.60

6.30

15.00

1. Evaluated by characterization. Not tested in production.

2. RTC with default configuration but LPCAL = 1 in RTC_CALR.

3. Current consumption with IWDG enabled is similar.

Table 67. 

Current consumption in Standby mode

 (continued)

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

-

V

DD

 (V)

25°C

55°C

85°C 105°C 125°C 30°C

55°C

85°C 105°C 125°C

Table 68. Current consumption during wake-up from Standby mode 

Symbol

Parameter

Conditions

Typ

(1)

Unit

-

V

DD

 (V)

25°C

Q

DD(wake-up from Standby)

Electrical charge consumed during wake-up from 
Standby mode

Wake-up clock is MSI 4 MHz

3.0

3.2

µAs

Wake-up clock is MSI 1 MHz

3.2

1. Evaluated by characterization in worse case condition (V

DD11 

/ V

CAP

 = 0 V before wake-up).

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Table 69. 

Current consumption in Shutdown mode 

 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

-

V

DD

 (V) 25°C 55°C 85°C 105°C 125°C

30°C

55°C

85°C

105°C 125°C

I

DD(Shutdown)

Supply current in 
Shutdown mode (backup 
registers retained), 
RTC disabled

-

1.8

0.16

0.62

2.65

7.05

18.50

0.49

1.60

6.70

18.00

47.00

µA

2.4

0.17

0.68

2.85

7.65

20.00

0.53

1.70

7.20

20.00

50.00

3.0

0.31

1.05

3.85

9.75

25.00

0.95

2.70

9.70

25.00

63.00

3.3

0.64

1.65

5.15 12.00 29.00

2.00

4.20

13.00

30.00

73.00

3.6

1.55

3.05

7.60 15.50 35.00

4.90

7.70

19.00

39.00

88.00

I

DD(Shutdown 

with RTC)

Supply current in 
Shutdown mode (backup 
registers retained), 
RTC enabled

RTC

(2)

 clocked by 

LSE bypassed at 
32768 Hz

1.8

0.33

0.80

2.85

7.25

19.00

0.67

1.80

6.90

18.00

47.00

2.4

0.37

0.88

3.10

7.85

20.50

0.75

2.00

7.40

20.00

51.00

3.0

0.57

1.30

4.15 10.00 25.50

1.30

2.90

10.00

25.00

64.00

3.3

0.94

2.00

5.50 12.50 29.50

2.40

4.60

14.00

31.00

74.00

3.6

1.90

3.45

8.00 16.00 35.50

5.20

8.10

20.00

40.00

89.00

RTC

(2)

 clocked by 

LSE quartz in 
low-drive mode

1.8

0.48

0.97

3.10

7.70

20.00

-

-

-

-

-

2.4

0.52

1.03

3.30

8.15

21.00

-

-

-

-

-

3.0

0.66

1.35

4.20 10.05 25.50

-

-

-

-

-

3.3

0.98

2.00

5.50 12.10 29.50

-

-

-

-

-

3.6

1.84

3.35

7.90 16.10 35.50

-

-

-

-

-

1. Evaluated by characterization. Not tested in production.

2. RTC with default configuration but LPCAL = 1 in RTC_CALR.

Table 70. Current consumption during wake-up from Shutdown mode 

Symbol

Parameter

Conditions

Typ

(1)

Unit

-

V

DD

 (V)

25°C

Q

DD(wake-up from 

Shutdown)

Electrical charge consumed during wake-up from 
Shutdown mode

Wake-up clock is MSI 4 MHz

3.0

3.4

μ

As

1. Evaluated by characterization in worse case condition (V

DD11

 / V

CAP

 = 0 V before wake-up).

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Table 71. 

Current consumption in V

BAT

 mode 

 

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

-

V

BAT

 (V) 25°C

55°C

85°C 105°C 125°C 30°C

55°C

85°C 105°C 125°C

I

DD(VBAT)

Supply current in V

BAT

 

mode (backup registers 
retained), 
RTC disabled

-

1.8

0.12

0.27

1.00

2.60

7.70

0.36

0.67

2.50

6.50

20.00

µA

2.4

0.13

0.29

1.05

2.70

8.10

0.39

0.72

2.70

6.80

21.00

3.0

0.16

0.37

1.30

3.20

9.10

0.50

0.93

3.30

8.00

23.00

3.3

0.25

0.56

1.80

4.25

11.50

0.78

1.40

4.50

11.00

29.00

3.6

0.46

0.89

2.35

5.00

13.00

1.50

2.30

5.90

13.00 33.00

I

DD(VBAT with 

RTC)

Supply current in V

BAT

 

mode (backup registers 
retained), 
RTC enabled

RTC

(2)

 clocked 

by LSE bypassed 
at 32768 Hz

1.8

0.40

0.56

1.30

2.80

7.65

0.68

0.99

2.90

6.80

20.00

2.4

0.48

0.65

1.45

3.05

8.30

0.78

1.20

3.10

7.20

21.00

3.0

0.62

0.85

1.80

3.75

9.65

1.10

1.50

3.80

8.70

24.00

3.3

0.78

1.10

2.35

4.90

12.50

1.40

2.00

5.20

12.00 30.00

3.6

1.10

1.55

3.00

5.80

13.50

2.20

3.00

6.60

14.00 34.00

RTC

(2)

 clocked 

by LSE bypassed 
at 32768 Hz, 
LPCAL = 1 in 
RTC_CALR

1.8

0.31

0.47

1.20

2.70

7.55

0.89

1.30

3.10

6.90

20.00

2.4

0.36

0.53

1.30

2.95

8.15

1.10

1.40

3.40

7.50

21.00

3.0

0.46

0.69

1.65

3.55

9.50

1.40

1.90

4.20

9.00

24.00

3.3

0.60

0.93

2.20

4.70

12.00

1.80

2.40

5.60

12.00 31.00

3.6

0.87

1.35

2.80

5.60

13.50

2.60

3.50

7.10

15.00 34.00

RTC

(2)

 clocked 

by LSE quartz in 
low-drive

1.8

0.54

0.71

1.45

3.05

8.35

-

-

-

-

-

2.4

0.60

0.77

1.55

3.25

8.70

-

-

-

-

-

3.0

0.69

0.91

1.85

3.75

9.70

-

-

-

-

-

3.3

0.80

1.10

2.35

4.90

12.60

-

-

-

-

-

3.6

1.05

1.50

2.95

5.70

13.60

-

-

-

-

-

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I

DD(VBAT with 

RTC)

Supply current in V

BAT

 

mode (backup registers 
retained), 
RTC enabled

RTC

(2)

 clocked 

by LSE quartz in 
low-drive mode, 
LPCAL = 1 in 
RTC_CALR

1.8

0.46

0.62

1.35

3.00

8.25

-

-

-

-

-

µA

2.4

0.48

0.66

1.45

3.10

8.55

-

-

-

-

-

3.0

0.53

0.76

1.70

3.60

9.55

-

-

-

-

-

3.3

0.63

0.95

2.20

4.70

12.10

-

-

-

-

-

3.6

0.85

1.30

2.75

5.50

13.60

-

-

-

-

-

I

DD(BKPSRAM)

Supply current to be added 
in V

BAT

 mode when backup 

SRAM is retained

-

1.8

0.12

0.19

0.41

0.85

1.75

0.26

0.44

1.10

2.50

5.20

2.4

0.12

0.19

0.45

0.95

1.90

0.26

0.45

1.30

2.80

5.60

3.0

0.12

0.20

0.50

1.05

2.40

0.28

0.49

1.40

3.10

7.10

3.3

0.13

0.22

0.50

1.10

2.50

0.31

0.54

1.40

3.20

7.40

3.6

0.14

0.22

0.50

1.20

2.50

0.36

0.55

1.40

3.50

7.40

1. Evaluated by characterization. Not tested in production.

2. RTC with default configuration except otherwise specified

Table 71. 

Current consumption in V

BAT

 mode 

 (continued)

Symbol

Parameter

Conditions

Typ

Max

(1)

Unit

-

V

BAT

 (V) 25°C

55°C

85°C 105°C 125°C 30°C

55°C

85°C 105°C 125°C

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DS13737 Rev 10

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up or pull-down generate current consumption when the 
pin is externally held to the opposite level. The value of this current consumption can be 
simply computed by using the pull-up/pull-down resistors values given in 

Section 5.3.15: I/O 

port characteristics

.

For the output pins, any internal or external pull-up or pull-down or external load must also 
be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate 
voltage level is externally applied. This current consumption is caused by the input Schmitt 
trigger circuits used to discriminate the input value. Unless this specific configuration is 
required by the application, this supply current consumption can be avoided by configuring 
these I/Os in analog mode. This is notably the case of the ADC input pins, that must be 
configured as analog inputs.

Caution:

Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, 
as a result of external electromagnetic noise. To avoid current consumption related to 
floating pins, they must either be configured in analog mode, or forced internally to a definite 
digital value. This can be done either by using pull-up/down resistors or by configuring the 
pins in output mode.

I/O dynamic current consumption

In addition to the on-chip peripheral current consumption (see 

Table 72

 for peripheral 

current consumption in Run mode), the I/Os used by an application also contribute to the 
current consumption. When an I/O pin switches, it uses the current from the I/O supply 
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal 
and external) connected to the pin:

where:

I

SW

 is the current sunk by a switching I/O to charge/discharge the capacitive load.

V

DDIOx

 is the I/O supply voltage.

f

SW

 is the I/O switching frequency.

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT 

+

 

C

S

.

C

S

 is the PCB board capacitance including the pad pin. 

The test pin is configured in push-pull output mode and is toggled by software at a fixed 
frequency.

I

SW

V

DDIOx

f

SW

C

×

×

=

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Electrical characteristics

305

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the table below. The MCU is 
placed under the following conditions:

All I/O pins are in analog mode.

The given value is calculated by measuring the difference of the current consumptions:

when the peripheral is clocked on

when the peripheral is clocked off

The ambient operating temperature and supply voltage conditions are summarized 
in 

Table 32

.

The power consumption of the digital part of the on-chip peripherals is given in the table 
below. The power consumption of the analog part of the peripherals (where applicable) 
is indicated in each related section of the datasheet.

          

Table 72. Typical dynamic current consumption of peripherals 

Bus

Peripheral

LDO

SMPS

Unit

Range1

Range2

Range3

Range4

Stop 1

Stop 2

Range1

Range2

Range3

Range4

Stop 1

Stop 2

AHB1

AHB1

1.81

1.64

1.48

1.34

-

0.87

0.74

0.61

0.48

-

µA/

MHz

BKPSRAM

0.90

0.80

0.74

0.67

-

0.44

0.37

0.31

0.24

-

CORDIC

0.56

0.51

0.45

0.41

-

0.27

0.23

0.19

0.15

-

CRC

0.34

0.30

0.27

0.25

-

0.17

0.14

0.12

0.09

-

DCACHE1

0.74

0.65

0.60

0.56

-

0.36

0.31

0.25

0.19

-

DMA2D

1.95

1.76

1.60

1.46

-

0.94

0.80

0.67

0.52

-

FLASH

2.21

2.01

1.82

1.65

-

1.07

0.91

0.76

0.59

-

FMAC

2.24

2.03

1.84

1.68

-

1.08

0.92

0.77

0.59

-

GPDMA1

3.71

3.38

3.05

2.75

-

1.80

1.52

1.27

0.98

-

GTZC1

0.39

0.34

0.31

0.30

-

0.18

0.16

0.13

0.10

-

ICACHE

0.76

0.68

0.63

0.57

-

0.37

0.32

0.26

0.20

-

MDF1

7.65

6.95

6.27

5.67

-

3.69

3.12

2.61

2.01

-

MDF1 indep

(1)

0.84

0.76

0.68

0.63

-

0.4

0.34

0.29

0.22

-

RAMCFG

1.26

1.14

1.03

0.96

-

0.61

0.52

0.43

0.33

-

SRAM1

0.82

0.73

0.67

0.62

-

0.40

0.34

0.28

0.22

-

TSC

1.11

1.00

0.91

0.83

-

0.54

0.46

0.38

0.29

-

AHB2-1

AHB2-1

2.08

1.88

1.71

1.54

-

1.00

0.85

0.71

0.55

-

ADC1

2.01

1.84

1.65

1.52

-

0.97

0.82

0.69

0.53

-

ADC1 indep

(1)

1.43

1.30

1.17

1.06

-

0.69

0.58

0.48

0.37

-

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DS13737 Rev 10

AHB2-

1

DCMI

4.68

4.28

3.87

3.50

-

2.26

1.92

1.61

1.24

-

µA/

MHz

GPIOA

0.08

0.07

0.07

0.05

-

0.04

0.03

0.03

0.02

-

GPIOB

0.06

0.05

0.04

0.04

-

0.03

0.02

0.02

0.01

-

GPIOC

0.11

0.11

0.08

0.08

-

0.05

0.05

0.04

0.03

-

GPIOD

0.07

0.07

0.06

0.06

-

0.04

0.03

0.03

0.02

-

GPIOE

0.04

0.05

0.03

0.03

-

0.02

0.02

0.01

0.01

-

GPIOF

0.07

0.08

0.06

0.05

-

0.04

0.03

0.03

0.02

-

GPIOG

0.22

0.21

0.17

0.16

-

0.11

0.09

0.07

0.05

-

GPIOH

0.22

0.21

0.17

0.17

-

0.11

0.09

0.07

0.06

-

GPIOI

0.12

0.13

0.10

0.09

-

0.06

0.05

0.04

0.03

-

HASH

1.18

1.10

0.98

0.88

-

0.57

0.49

0.41

0.31

-

OCTOSPIM

0.25

0.23

0.20

0.18

-

0.09

0.07

0.06

0.05

-

RNG

0.82

0.76

0.67

0.60

-

0.39

0.33

0.28

0.21

-

RNG indep

(1)

0.10

0.06

0.06

0.06

-

0.06

0.02

0.02

0.02

-

SDMMC1

12.26 11.18 10.11

9.15

-

5.92

5.01

4.20

3.24

-

SDMMC1 indep

(1)

1.47

1.34

1.22

1.09

-

0.71

0.60

0.50

0.40

-

SDMMC2

12.48 11.39 10.29 9.31

-

6.02

5.10

4.28

3.30

-

SDMMC2 indep

(1)

1.59

1.44

1.31

1.18

-

0.76

0.65

0.54

0.44

-

SRAM2

1.18

1.10

0.97

0.88

-

0.57

0.48

0.40

0.32

-

SRAM3

1.31

1.22

1.07

0.97

-

0.63

0.54

0.45

0.35

-

USB_OTG_FS

10.47 9.58

8.67

7.83

-

5.05

4.30

3.61

2.77

-

AHB2-2

AHB2-2

0.79

0.74

0.64

0.58

-

0.38

0.32

0.26

0.20

-

FMC

5.34

4.87

4.42

3.99

-

2.58

2.19

1.84

1.42

-

OCTOSPI1

0.79

0.72

0.65

0.58

-

0.39

0.32

0.28

0.21

-

OCTOSPI1 indep

(1)

1.11

1.01

0.91

0.83

-

0.54

0.45

0.38

0.29

-

OCTOSPI2

0.79

0.72

0.65

0.58

-

0.39

0.32

0.28

0.21

-

OCTOSPI2 indep

(1)

0.91

0.83

0.75

0.68

-

0.44

0.37

0.31

0.24

-

Table 72. Typical dynamic current consumption of peripherals (continued)

Bus

Peripheral

LDO

SMPS

Unit

Ra

nge1

Ra

nge2

Ra

nge3

Ra

nge4

Stop 1

Stop 2

Ra

nge1

Ra

nge2

Ra

nge3

Ra

nge4

Stop 1

Stop 2

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Electrical characteristics

305

AH

B

3

ADC4

0.96

0.87

0.79

0.72

0.98

0.46

0.39

0.33

0.26

0.35

µA/

MHz

ADC4 indep

(1)

2.52

2.28

2.06

1.85

1.86

1.21

1.03

0.86

0.66

0.66

ADF1

0.97

0.87

0.79

0.72

0.97

0.47

0.39

0.33

0.25

0.34

ADF1 indep

(1)

0.35

0.31

0.28

0.26

0.21

0.17

0.14

0.12

0.09

0.07

AHB3

0.34

0.34

0.28

0.24

-

0.17

0.14

0.11

0.09

-

DAC1

1.88

1.70

1.55

1.39

1.66

0.91

0.76

0.64

0.50

0.59

DAC1 indep

(1)

1.30

1.17

1.06

0.96

0.92

0.63

0.52

0.44

0.34

0.33

GTZC2

0.34

0.32

0.30

0.29

-

0.16

0.14

0.12

0.11

-

LPDMA1

0.43

0.39

0.36

0.32

0.58

0.21

0.17

0.14

0.11

0.20

LPGPIO1

0.10

0.09

0.09

0.08

0.26

0.05

0.04

0.03

0.03

0.09

PWR

0.13

0.12

0.10

0.09

-

0.06

0.05

0.04

0.03

-

SRAM4

0.45

0.40

0.37

0.34

0.26

0.21

0.18

0.15

0.12

0.09

APB1

APB1

1.50

1.39

1.23

1.10

-

0.73

0.61

0.51

0.40

-

CRS

0.30

0.27

0.25

0.22

-

0.15

0.12

0.10

0.08

-

FDCAN1

5.09

4.64

4.21

3.79

-

2.46

2.08

1.75

1.35

-

FDCAN1 indep

(1)

2.70

2.41

2.20

1.99

-

1.30

1.10

0.93

0.71

-

I2C1

0.98

0.90

0.81

0.72

-

0.48

0.40

0.34

0.26

-

I2C1 indep

(1)

2.26

2.06

1.86

1.69

-

1.09

0.92

0.78

0.59

-

I2C2

3.24

2.95

2.67

2.40

-

1.57

1.33

1.11

0.86

-

I2C2 indep

(1)

2.30

2.09

1.90

1.72

-

1.11

0.94

0.79

0.61

-

I2C4

1.26

1.15

1.04

0.92

-

0.61

0.52

0.43

0.33

-

I2C4 indep

(1)

2.43

2.21

2.00

1.81

-

1.17

0.99

0.84

0.64

-

Table 72. Typical dynamic current consumption of peripherals (continued)

Bus

Peripheral

LDO

SMPS

Unit

Ra

nge1

Ra

nge2

Ra

nge3

Ra

nge4

Stop 1

Stop 2

Ra

nge1

Ra

nge2

Ra

nge3

Ra

nge4

Stop 1

Stop 2

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Electrical characteristics

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DS13737 Rev 10

APB1

LPTIM2

1.71

1.56

1.42

1.26

-

0.83

0.70

0.59

0.46

-

µA/

MHz

LPTIM2 indep

(1)

4.20

3.83

3.48

3.15

-

2.03

1.72

4.95

1.11

-

SPI2

1.90

1.73

1.57

1.40

-

0.92

0.77

0.66

0.51

-

SPI2 indep

(1)

0.81

0.75

0.68

0.62

-

0.40

0.33

0.28

0.21

-

TIM2

4.01

3.64

3.31

2.99

-

1.93

1.64

1.37

1.06

-

TIM3

4.51

4.10

3.72

3.35

-

2.18

1.84

1.55

1.19

-

TIM4

4.27

3.88

3.52

3.16

-

2.06

1.74

1.46

1.12

-

TIM5

3.95

3.60

3.27

2.93

-

1.91

1.62

1.36

1.04

-

TIM6

0.95

0.86

0.78

0.69

-

0.46

0.39

0.33

0.25

-

TIM7

0.90

0.82

0.75

0.65

-

0.44

0.37

0.31

0.24

-

UART4

1.86

1.70

1.54

1.39

-

0.90

0.76

0.64

0.50

-

UART4 indep

(1)

3.47

3.17

2.87

2.60

-

1.68

1.42

1.19

0.93

-

UART5

1.93

1.76

1.60

1.44

-

0.94

0.79

0.66

0.51

-

UART5 indep

(1)

3.57

3.25

2.95

2.67

-

1.72

1.46

1.23

0.95

-

UCPD1

1.60

1.46

1.33

1.17

-

0.78

0.66

0.55

0.43

-

USART2

5.53

5.04

4.57

4.12

-

2.67

2.26

1.91

1.46

-

USART2 indep

(1)

3.57

3.24

2.95

2.65

-

1.72

1.46

1.22

0.94

-

USART3

2.10

1.91

1.73

1.57

-

1.02

0.86

0.72

0.56

-

USART3 indep

(1)

4.24

3.86

3.5

3.17

-

2.05

1.73

1.45

1.12

-

WWDG

0.37

0.34

0.31

0.25

-

0.18

0.15

0.13

0.10

-

APB2

APB2

0.60

0.58

0.50

0.42

-

0.29

0.25

0.20

0.16

-

SAI1

2.10

1.90

1.73

1.55

-

1.01

0.86

0.72

0.55

-

SAI1 indep

(1)

1.36

1.23

1.11

0.95

-

0.66

0.55

0.46

0.34

-

SAI2

1.98

1.80

1.64

1.48

-

0.96

0.81

0.68

0.53

-

SAI2 indep

(1)

1.25

1.14

1.02

0.92

-

0.60

0.51

0.43

0.40

-

SPI1

2.17

1.97

1.79

1.63

-

1.05

0.89

0.75

0.57

-

Table 72. Typical dynamic current consumption of peripherals (continued)

Bus

Peripheral

LDO

SMPS

Unit

Ra

nge1

Ra

nge2

Ra

nge3

Ra

nge4

Stop 1

Stop 2

Ra

nge1

Ra

nge2

Ra

nge3

Ra

nge4

Stop 1

Stop 2

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APB2

SPI1 indep

(1)

0.97

0.88

0.79

0.72

-

0.47

0.39

0.33

0.25

-

µA/

MHz

TIM1

6.14

5.59

5.08

4.60

-

2.96

2.52

2.11

1.63

-

TIM15

3.37

3.06

2.79

2.51

-

1.63

1.38

1.16

0.89

-

TIM16

2.60

2.36

2.15

1.94

-

1.25

1.06

0.90

0.69

-

TIM17

2.40

2.18

1.99

1.79

-

1.16

0.98

0.82

0.63

-

TIM8

6.24

5.69

5.16

4.66

-

3.01

2.55

2.15

1.65

-

USART1

2.38

2.16

1.96

1.76

-

1.14

0.97

0.81

0.62

-

USART1 indep

(1)

4.48

4.09

3.71

3.35

-

2.17

1.84

1.54

1.19

-

APB3

APB3

0.49

0.48

0.40

0.36

-

0.24

0.20

0.16

0.13

-

COMP

0.20

0.18

0.16

0.14

0.15

0.10

0.08

0.06

0.05

0.05

I2C3

0.79

0.71

0.65

0.58

0.59

0.38

0.32

0.27

0.20

0.21

I2C3 indep

(1)

1.84

1.66

1.50

1.36

1.36

0.89

0.75

0.63

0.48

0.48

LPTIM1

0.98

0.89

0.81

0.72

0.73

0.48

0.40

0.33

0.25

0.26

LPTIM1 indep

(1)

3.08

2.81

2.49

2.29

2.33

1.46

1.24

1.04

0.81

0.83

LPTIM3

1.07

0.98

0.89

0.80

0.80

0.52

0.44

0.37

0.28

0.28

LPTIM3 indep

(1)

2.85

2.61

2.36

2.15

2.19

1.43

1.22

0.98

0.77

0.78

LPTIM4

0.58

0.52

0.48

0.42

0.43

0.28

0.24

0.20

0.15

0.15

LPTIM4 indep

(1)

1.67

1.50

1.38

1.26

1.30

0.8

0.70

0.57

0.44

0.46

LPUART1

1.18

1.07

0.97

0.87

0.88

0.57

0.48

0.41

0.31

0.31

LPUART1 indep

(1)

1.96

1.78

1.62

1.45

1.46

0.95

0.80

0.67

0.52

0.52

OPAMP

0.19

0.17

0.16

0.12

0.14

0.09

0.07

0.07

0.04

0.05

RTC

2.33

2.12

1.92

1.73

1.63

1.12

0.95

0.80

0.61

0.58

SPI3

1.48

1.34

1.22

1.10

1.10

0.71

0.61

0.51

0.38

0.39

SPI3 indep

(1)

0.57

0.52

0.47

0.42

0.42

0.28

0.24

0.20

0.15

0.15

SYSCFG

0.29

0.27

0.24

0.22

-

0.14

0.12

0.10

0.08

-

VREFBUF

0.13

0.11

0.10

0.08

0.09

0.06

0.05

0.04

0.03

0.03

1.

indep = independent clock domain.

Table 72. Typical dynamic current consumption of peripherals (continued)

Bus

Peripheral

LDO

SMPS

Unit

Ra

nge1

Ra

nge2

Ra

nge3

Ra

nge4

Stop 1

Stop 2

Ra

nge1

Ra

nge2

Ra

nge3

Ra

nge4

Stop 1

Stop 2

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DS13737 Rev 10

5.3.7 

Wake-up time from low-power modes and voltage scaling

 

transition times

The wake-up times given in the table below are the latency between the event and the 
execution of the first user instruction (FSTEN = 1 in PWR_CR3 if not mentioned).

The device goes in low-power mode after the WFE (wait for event) instruction.

          

Table 73. Low-power mode wake-up timings on LDO

(1)

 

Mode

Parameter

Conditions

Typ

(3 V, 25 °C)

Max 

(3 V)

Unit

t

wu(Sleep)

Wake-up time from 
Sleep to Run mode

SLEEP_PD = 0

14

17

Nb of 

CPU 

cycles

SLEEP_PD = 1 with MSI = 24 MHz

8.1

8.8

µs

t

wu(Stop 0)

Wake-up time from 
Stop 0 to Run mode
All SRAMs retained

Wake-up in FLASH, 
range 4, FLASHFWU = 1 
and SRAM4FWU = 1 in 
PWR_CR2, ICACHE OFF

MSI 24 MHz

2.35

2.5

Wake-up in FLASH, 
range 4, FLASHFWU = 0 
and SRAM4FWU = 0 in 
PWR_CR2, ICACHE OFF

MSI 24 MHz

11.0

12.0

HSI 16 MHz

11.0

12.0

MSI 1 MHz

37.0

39.0

Wake-up in SRAM2, 
range 4, FLASHFWU = 0 
and SRAM4FWU = 0 in 
PWR_CR2

MSI 24 MHz

4.75

5.00

HSI 16 MHz

6.75

7.4

MSI 1 MHz

34.00

36.0

t

wu(Stop 1)

Wake-up time from 
Stop 1 to Run mode
All SRAMs retained

Wake-up in FLASH, 
FLASHFWU = 1 and 
SRAM4FWU = 1 in 
PWR_CR2, ICACHE OFF

MSI 24 MHz

13.0

15.0

Wake-up in FLASH, 
FLASHFWU = 0 and 
SRAM4FWU = 0 in 
PWR_CR2, ICACHE OFF

MSI 24 MHz

22.0

24.0

HSI 16 MHz

21.5

24.0

MSI 1 MHz

48.0

51.0

Wake-up in SRAM2, 
range 4, FLASHFWU = 0 
and SRAM4FWU = 0 in 
PWR_CR2

MSI 24 MHz

15.5

18.0

HSI 16 MHz

17.5

20.0

MSI 1 MHz

45.0

48.0

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t

wu(Stop 2)

Wake-up time from 
Stop 2 to Run mode
All SRAMs retained

Wake-up in FLASH, 
SRAM4FWU = 1 in 
PWR_CR2, ICACHE OFF

MSI 24 MHz

20.0

23.0

µs

Wake-up in FLASH, 
SRAM4FWU = 0 in 
PWR_CR2, ICACHE OFF

MSI 24 MHz

23.0

25.0

(2)

HSI 16 MHz

22.5

25.0

MSI 1 MHz

57.0

60.0

Wake-up in SRAM2, 
range 4, SRAM4FWU = 0 
in PWR_CR2

MSI 24 MHz

16.5

19.0

HSI 16 MHz

18.5

21.0

MSI 1 MHz

54.0

57.0

t

wu(Stop 3)

Wake-up time from 
Stop 3 to Run mode
All SRAMs retained

Wake-up in FLASH,

 

FSTEN = 0 in PWR_CR3, 
ICACHE OFF

MSI 24 MHz

68.0

130

Wake-up in FLASH,

 

FSTEN = 1 in PWR_CR3, 
ICACHE OFF

MSI 24 MHz

28.50

37.0

HSI 16 MHz

28.0

36.0

MSI 1 MHz

68.50

91.0

Wake-up in SRAM2, 
range 4, FLASHFWU = 0 
and SRAM4FWU = 0 in 
PWR_CR2

MSI 24 MHz

22.50

31.0

HSI 16 MHz

24.0

32.0

MSI 1 MHz

64.5

85.0

t

wu(Standby 

with SRAM2)

Wake-up time from 
Standby with SRAM2 
to Run mode

Wake-up in FLASH,

 

FSTEN = 0 in PWR_CR3

MSI 4 MHz

64.5

110

Wake-up in FLASH,

 

FSTEN = 1 in PWR_CR3

MSI 4 MHz

64.5

83.0

MSI 1 MHz

155

240

t

wu(Standby)

Wake-up time from 
Standby to Run mode

Wake-up in FLASH,

 

FSTEN = 0 in PWR_CR3

MSI 4 MHz

340

420

Wake-up in FLASH,

 

FSTEN = 1 in PWR_CR3

MSI 4 MHz

100

130

MSI 1 MHz

210

290

t

wu(Shutdown)

Wake-up time from 
Shutdown to Run mode

-

MSI 4 MHz

610

710

1. Evaluated by characterization and not tested in production, unless otherwise specified.

2. Tested in production at 130°C.

Table 73. Low-power mode wake-up timings on LDO

(1)

 (continued)

Mode

Parameter

Conditions

Typ

(3 V, 25 °C)

Max 

(3 V)

Unit

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Table 74. Low-power mode wake-up timings on SMPS

(1)

 

Mode

Parameter

Conditions

Typ

(3 V, 

25 °C)

Max 

(3 V)

Unit

t

wu(Sleep)

Wake-up time from Sleep 
to Run mode

SLEEP_PD = 0

14

17

Nb of 

CPU 

cycles

SLEEP_PD = 1 with MSI = 24 MHz

8.1

8.8

µs

t

wu(Stop 0)

Wake-up time from 
Stop 0 to Run mode
All SRAMs retained

Wake-up in FLASH, range 4, 
FLASHFWU = 1 and 
SRAM4FWU = 1 in 
PWR_CR2

MSI 24 MHz

2.35

2.5

Wake-up in FLASH, range 4, 
FLASHFWU = 0 and 
SRAM4FWU = 0 in 
PWR_CR2

MSI 24 MHz

11.0

12.0

HSI 16 MHz

11.0

12.0

MSI 1 MHz

37.0

39.0

Wake-up in SRAM2, range 4, 
FLASHFWU = 0 and 
SRAM4FWU = 0 in 
PWR_CR2

MSI 24 MHz

4.75

5.0

HSI 16 MHz

6.75

7.4

MSI 1 MHz

34.0

36.0

t

wu(Stop 1)

Wake-up time from 
Stop 1 to Run mode
All SRAMs retained

Wake-up in FLASH, 
FLASHFWU = 1 and 
SRAM4FWU = 1 in 
PWR_CR2

MSI 24 MHz

7.7

8.3

Wake-up in FLASH 
FLASHFWU = 0 and 
SRAM4FWU = 0 in 
PWR_CR2

MSI 24 MHz

16.5

18.0

HSI 16 MHz

16.0

18.0

MSI 1 MHz

42.5

45.0

Wake-up in SRAM2, range 4, 
FLASHFWU = 0 and 
SRAM4FWU = 0 in 
PWR_CR2

MSI 24 MHz

10.0

11.0

HSI 16 MHz

12.0

13.0

MSI 1 MHz

39.5

42.0

t

wu(Stop 2)

Wake-up time from 
Stop 2 to Run mode
All SRAMs retained

Wake-up in FLASH 
SRAM4FWU = 1 in 
PWR_CR2

MSI 24 MHz

17.5

19.0

Wake-up in FLASH 
SRAM4FWU = 0 in 
PWR_CR2

MSI 24 MHz

20.5

22.0

HSI 16 MHz

20.0

22.0

MSI 1 MHz

54.0

70.0

Wake-up in SRAM2, range 4, 
SRAM4FWU = 0 in 
PWR_CR2

MSI 24 MHz

14.0

16.0

HSI 16 MHz

16.0

18.0

MSI 1 MHz

51.5

74.0

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t

wu(Stop 3)

Wake-up time from 
Stop 3 to Run mode
All SRAMs retained

Wake-up in FLASH,

 

FSTEN = 0 in PWR_CR3

MSI 24 MHz

130

160

µs

Wake-up in FLASH,

 

FSTEN = 1 in PWR_CR3

MSI 24 MHz

32.5

37.0

HSI 16 MHz

32.0

36.0

MSI 1 MHz

72.5

94.0

Wake-up in SRAM2, range 4

MSI 24 MHz

26.5

31.0

HSI 16 MHz

28.0

32.0

MSI 1 MHz

68.5

89.0

t

wu(Standby 

with SRAM2)

Wake-up time from 
Standby with SRAM2 to 
Run mode

Wake-up in FLASH,

 

FSTEN = 0 in PWR_CR3

MSI 4 MHz

61.5

80.0

Wake-up in FLASH,

 

FSTEN = 1 in PWR_CR3

MSI 4 MHz

61.5

80.0

MSI 1 MHz

150

240

t

wu(Standby)

Wake-up time from 
Standby to Run mode

Wake-up in FLASH,

 

FSTEN = 0 in PWR_CR3

MSI 4 MHz

340

420

Wake-up in FLASH,

 

FSTEN = 1 in PWR_CR3

MSI 4 MHz

100

130

MSI 1 MHz

210

290

t

wu(Shutdown)

Wake-up time from 
Shutdown to Run mode

-

MSI 4 MHz

610

710

1. Evaluated by characterization. Not tested in production.

Table 74. Low-power mode wake-up timings on SMPS

(1)

 (continued)

Mode

Parameter

Conditions

Typ

(3 V, 

25 °C)

Max 

(3 V)

Unit

Table 75. Regulator mode transition times

(1)

 

Symbol

Parameter

Conditions

Typ (3 V, 25 °C)

Max (3 V)

Unit

t

LDO

(2)

SMPS to LDO transition time

Range 4

16.0

20.0

(3)

µs

Range 3

15.0

17.0

Range 2

14.0

18.0

Range 1

14.0

16.0

t

SMPS

(2)

LDO to SMPS transition time

Range 4

14.0

16.0

(3)

Range 3

17.0

20.0

Range 2

16.0

19.0

Range 1

16.0

19.0

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5.3.8 External 

clock 

timing characteristics

High-speed external user clock generated from an external source

In bypass mode, the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in 

Section 5.3.15: I/O port 

characteristics

. However, the recommended clock input waveform is shown in the figure 

below.

          

t

VOST

(4)

Range 4 to range 3

LDO

19.0

21.0

µs

SMPS

25.0

38.0

Range 3 to range 2

LDO

13.0

15.0

SMPS

13.0

23.0

Range 2 to range 1

LDO

12.0

14.0

SMPS

12.0

17.0

Range 4 to range 1

LDO

42.0

47.0

SMPS

48.0

76.0

1. Evaluated by characterization and not tested in production, unless otherwise specified. 

2. Time to REGS change in PWR_SVMSR.

3. Tested in production at 30°C.

4. Time to VOSRDY = 1 in PWR_VOSR.

Table 75. Regulator mode transition times

(1)

 (continued)

Symbol

Parameter

Conditions

Typ (3 V, 25 °C)

Max (3 V)

Unit

Table 76. Wake-up time using USART/LPUART

(1)

 

Symbol

Parameter

Typ

Max

Unit

t

WUUSART 

t

WULPUART

Wake-up time needed to calculate the maximum USART/LPUART baud rate that 
is needed to wake up from Stop mode when the USART/LPUART kernel clock 
source is HSI16/MSI.

-

(2)

μ

s

1. Specified by design. Not tested in production.

2. This wake-up time is the HSI16 (see 

Table 81

) or the MSI (see 

Table 82

) oscillator maximum startup time.

Table 77. High-speed external user clock characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f

HSE_ext

User external clock 
source frequency

Digital mode 
(HSEBYP = 1, 
HSEEXT = 1)

Voltage scaling 
range 1, 2, 3

-

-

55

MHz

Analog mode 
(HSEBYP = 1, 
HSEEXT = 0)

4

(2)

-

50

-

Voltage scaling 
range 4

4

(2)

-

25

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Figure 28. AC timing diagram for high-speed external clock source (digital mode)

V

HSEH

OSC_IN input pin 
high-level voltage

Digital mode 
(HSEBYP = 1, 
HSEEXT = 1)

-

0.7 × V

DD

-

V

DD

V

V

HSEL

OSC_IN input pin 
low-level voltage

-

V

SS

-

0.3  ×  V

DD

t

w(HSEH) 

t

w(HSEL)

OSC_IN high or low time

Voltage scaling 
range 1, 2, 3

7

-

-

ns

Voltage scaling 
range 4

18

-

-

DuCy

HSE

 OSC_IN 

duty 

cycle

-

45

-

55

%

V

HSE_ext_

PP

 

OSC_IN peak-to-peak 
amplitude 

Analog mode 
(HSEBYP = 1, 
HSEEXT = 0)

-

0.2

-

2/3 V

DD

V

V

HSE_ext 

OSC_IN input range

-

0

-

V

DD

t

r(HSE), 

tf(HSE)

 

OSC_IN rise and fall time

-

0.05 / 

f

HSE_ext

-

0.3 / 

f

HSE_ext

ns

1. Specified by design. Not tested in production.

2. Only for Analog mode. No minimum value in digital mode.

Table 77. High-speed external user clock characteristics

(1)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MSv67850V3

V

HSEH

70%

30%

T

HSE

t

V

HSEL

t

w(HSEH)

t

w(HSEL)

V

HSE

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Figure 29. AC timing diagram for high-speed external clock source (analog mode)

Low-speed external user clock generated from an external source

In bypass mode, the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in 

Section 5.3.15: I/O port 

characteristics

. However, the recommended clock input waveform is shown in 

Figure 30

 

and 

Figure 31

.

          

Figure 30. AC timing diagram for low-speed external square clock source

MSv71538V1

V

HSE_ext

V

HSE_ext_PP

t

t

HSE_ext

 = 1/f

HSE_ext

90%

10%

t

f(HSE)

t

r(HSE)

Table 78. Low-speed external user clock characteristics

(1)

 

Symbol

Parameter

Min

Typ

Max

Unit

f

LSE_ext

User external clock source frequency

5

32.768

40

kHz

V

LSE_ext_PP

OSC32_IN peak-to-peak amplitude

0.3

-

V

SW

V

V

LSE_ext

OSC32_IN input range

0

-

V

SW

(2)

t

w(LSEH) 

t

w(LSEL)

OSC32_IN high or low time for square signal input

10

-

-

μ

s

1. Specified by design. Not tested in production.

2. In case VBAT mode is used, V

LSE_ext 

must be lower than V

BOR0

 in order to respect this requirement when the switch to 

VBAT occurs.

MSv67851V3

V

LSEH

70%

30%

t

V

LSEL

t

w(LSEH)

t

w(LSEL)

V

LSE_ext

t

LSE

 = 1/f

LSE_ext

V

LSE_ext_PP

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Figure 31. AC timing diagram for low-speed external sinusoidal clock source

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic 
resonator oscillator. All the information given in this paragraph are based on design 
simulation results obtained with typical external components specified in the table below.

In the application, the resonator and the load capacitors have to be placed as close as 
possible to the oscillator pins, in order to minimize the output distortion and startup 
stabilization time. Refer to the crystal resonator manufacturer for more details on the 
resonator characteristics (frequency, package, accuracy).

          

MSv69160V1

V

LSE_ext

V

LSE_ext_PP

t

t

LSE_ext

 = 1/f

LSE_ext

Table 79. HSE oscillator characteristics

(1)

 

Symbol

Parameter

Conditions

(2)

Min

Typ

Max Unit

f

OSC_IN

Oscillator 
frequency

-

4

-

50

MHz

R

F

Feedback resistor

-

-

200

-

k

I

DD(HSE)

HSE current 
consumption

Rev. X

During startup

(3)

-

-

8

mA

V

DD

 = 3 V, Rm = 30 

, C

L

 = 10 pF @ 4 MHz

-

670

-

μ

A

V

DD

 = 3 V, Rm = 30 

, C

L

 = 10 pF @ 8 MHz

-

530

-

V

DD

 = 3 V, Rm = 45 

, C

L

 = 10 pF @ 8 MHz

-

580

-

V

DD

 = 3 V, Rm = 30 

, C

L

 = 5 pF @ 48 MHz

-

980

-

V

DD

 = 3 V, Rm = 30 

, C

L

 = 10 pF @ 48 MHz

-

1700

-

V

DD

 = 3 V, Rm = 30 

, C

L

 = 20 pF @ 48 MHz

-

2700

-

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DS13737 Rev 10

Note:

For information on selecting the crystal, refer to the application note ‘Oscillator design guide 
for STM8AF/AL/S, STM32 MCUs and MPUs’ (AN2867).

Figure 32. Typical application with a 8 MHz crystal

1. R

EXT

 value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator 
oscillator. All the information given in this paragraph are based on design simulation results 
obtained with typical external components specified in the table below. In the application, 
the resonator and the load capacitors have to be placed as close as possible to the 

I

DD(HSE)

HSE current 
consumption

Other 
revisions

During startup

(3)

-

-

8

mA

V

DD

 = 3 V, Rm = 30 

, C

L

 = 10 pF @ 4 MHz

-

790

-

μ

A

V

DD

 = 3 V, Rm = 30 

, C

L

 = 10 pF @ 8 MHz

-

910

-

V

DD

 = 3 V, Rm = 45 

, C

L

 = 10 pF @ 8 MHz

-

930

-

V

DD

 = 3 V, Rm = 30 

, C

L

 = 5 pF @ 48 MHz

-

1430

-

V

DD

 = 3 V, Rm = 30 

, C

L

 = 10 pF @ 48 MHz

-

1960

-

V

DD

 = 3 V, Rm = 30 

, C

L

 = 20 pF @ 48 MHz

-

3000

-

Gm

critmax 

Maximum critical 
crystal 
transconductance 
G

m

Startup

-

-

1.5 mA/V

t

su(HSE)

(4)

Startup time

 V

DD

 stabilized

-

2

-

ms

1. Specified by design. Not tested in production.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE) 

startup time.

4. t

SU(HSE)

 is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is 

reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Table 79. HSE oscillator characteristics

(1)

 (continued)

Symbol

Parameter

Conditions

(2)

Min

Typ

Max Unit

MS19876V1

(1)

OSC_IN

OSC_OUT

R

F

Bias 

controlled 

gain

f

HSE

R

EXT

8 MHz 

resonator

Resonator with integrated 
capacitors

C

L1

C

L2

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305

oscillator pins in order to minimize output distortion and startup stabilization time. Refer to 
the crystal resonator manufacturer for more details on the resonator characteristics 
(frequency, package, accuracy).

          

Note:

For information on selecting the crystal, refer to the application note ‘Oscillator design guide 
for STM8AF/AL/S, STM32 MCUs and MPUs’ (AN2867).

Figure 33. Typical application with a 32.768 kHz crystal

Note:

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden 
to add one.

Table 80. LSE oscillator characteristics (f

LSE

 = 32.768 kHz)

(1)

 

Symbol

Parameter

Conditions

(2)

Min

Typ

Max Unit

I

DD(LSE)

LSE current 
consumption

Rev. X

LSEDRV[1:0] = 01, medium low-drive capability

-

350

-

nA

LSEDRV[1:0] = 10, medium high-drive capability

-

450

-

LSEDRV[1:0] = 11, high-drive capability

-

600

-

Other 
revisions

LSEDRV[1:0] = 00, low-drive capability

-

410

-

LSEDRV[1:0] = 01, medium low-drive capability

450

LSEDRV[1:0] = 10, medium high-drive capability

-

590

-

LSEDRV[1:0] = 11, high-drive capability

-

700

-

Gm

critmax

Maximum 
critical crystal 
Gm

LSEDRV[1:0] = 00, low-drive capability

-

-

0.5

µA/V

LSEDRV[1:0] = 01, medium low-drive capability

-

-

0.75

LSEDRV[1:0] = 10, medium high-drive capability

-

-

1.7

LSEDRV[1:0] = 11, high-drive capability

-

-

2.7

C

S_PARA

Internal stray 
parasitic 
capacitance

(3)

Rev. X

-

5

-

pF

Other 
revisions

-

-

3

-

t

SU(LSE)

(4)

Startup time

V

DD

 is stabilized

-

2

-

s

1. Specified by design. Not tested in production.

2. Refer to the note below this table.

3. C

S_PARA

 is the equivalent capacitance seen by the crystal due to OSC32_IN and OSC32_OUT internal parasitic 

capacitances.

4.  t

SU(LSE)

 is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is 

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

MSv70418V1

OSC32_IN

OSC32_OUT

Drive 

programmable 

amplifier

f

LSE

32.768 kHz resonator

Resonator with integrated capacitors

C

L1

C

L2

C

S

Note: 

CL1 and CL2 are external load capacitanc

es. Cs (stray capacitance) is the sum of the device OSC32_IN/OSC32_OUT pins

          equivalent parasitic capacitance (C

S_PARA

), and the PCB parasitic capacitance.  

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Electrical characteristics

STM32U575xx

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DS13737 Rev 10

5.3.9 Internal 

clock 

timing characteristics

The parameters given in the table below are derived from tests performed under ambient 
temperature and supply voltage conditions summarized in 

Table 32

. The provided curves 

are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

          

Figure 34. HSI16 frequency versus temperature and V

DD

Table 81. HSI16 oscillator characteristics 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f

HSI16

HSI16 frequency after factory 
calibration

V

DD 

= 3.0 V, T

= 30 °C

15.92

16

16.08

MHz

f

HSI16

(1)

T

= –10 °C to 100 °C, 

1.58 

 V

DD

 

 3.6 V

15.84

-

16.16

T

= –40 °C to 130 °C, 

1.58 

 V

DD

 

 3.6 V

15.65

-

16.25

TRIM

HSI16

(2)

HSI16 user trimming step

-

18

29

40

kHz

DuCy

HSI16

(2)

Duty cycle

-

45

-

55

%

t

su(HSI16)

(2)

HSI16 oscillator startup time

-

-

2.5

3.6

μ

s

t

stab(HSI16)

(2)

HSI16 oscillator stabilization time

At 1% of target frequency

-

4

6

I

DD(HSI16)

(2)

HSI16 oscillator power consumption

-

-

150

210

μ

A

1. Evaluated by characterization. Not tested in production. It does not take into account package and soldering effects.

2. Specified by design. Not tested in production.

MSv75106V1

15.65

15.85

15.92

15.91

15.87

15.8

15.68

16.25

16.16

16.08

16.11

16.15

16.17

16.2

-40

-20

0

20

40

60

80

100

120

Frequency (MHz)

Temperature (°C)

+/-1%

HSI16 min freq

HSI16 max freq

temp +/-1%

-2%

15.65

15.7

15.75

15.8

15.85

15.9

15.95

16

16.05

16.1

16.15

16.2

16.25

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DS13737 Rev 10

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STM32U575xx

Electrical characteristics

305

Multi-speed internal (MSI) RC oscillator

          

Table 82. MSI oscillator characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f

MSI

MSI frequency 
after factory 
calibration

V

DD

 = 3 V 

T

J

 = 30 °C

MSI mode

MSI range 0 
(MSIRC0)

47.74

48

48.70

MHz

MSI range 1

23.87

24

24.35

MSI range 2

15.91

16

16.23

MSI range 3

11.93

12

12.17

MSI range 4 
(MSIRC1)

3.98

4

4.06

MSI range 5

1.99

2

2.03

MSI range 6

1.33

1.33

1.35

MSI range 7

0.99

1

1.01

MSI range 8 
(MSIRC2)

3.05

3.08

3.12

MSI range 9

1.53

1.54

1.56

MSI range 10

1.02

1.03

1.04

MSI range 11

0.76

0.77

0.78

MSI range 12 
(MSIRC3)

397.68

400

405.71

kHz

MSI range 13

198.84

200

202.86

MSI range 14

132.56

133

135.24

MSI range 15

99.42

100

101.43

PLL 
mode

(2)

XTAL =

 

32.768 kHz

MSI range 0 
(MSIRC0)

-

48.005

-

MHz

MSI range 1

-

24.003

-

MSI range 2

-

16.002

-

MSI range 3

-

12.001

-

MSI range 4 
(MSIRC1)

-

3.998

-

MSI range 5

-

1.999

-

MSI range 6

-

1.333

-

MSI range 7

-

0.999

-

MSI range 8 
(MSIRC2)

-

3.08

-

MSI range 9

-

1.54

-

MSI range 10

-

1.027

-

MSI range 11

-

0.77

-

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Electrical characteristics

STM32U575xx

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DS13737 Rev 10

f

MSI (cont’d)

MSI frequency 
after factory 
calibration

V

DD

 = 3 V 

T

J

 = 30 °C

PLL mode
XTAL =

 

32.768 kHz

MSI range 12 
(MSIRC3)

-

393

-

kHz

MSI range 13

-

196.6

-

MSI range 14

-

131

-

MSI range 15

-

98.3

-

DuCy

MSI

(3)

Duty cycle

MSI range 0, 4, 8, or 12

38

-

62

%

MSI range 2, 6, 10, or 14

31

-

69

Other MSI ranges

48

-

52

TRIM

MSI

User trimming 
step

-

-

0.4

-

TEMP(MSI)

(4)

MSI oscillator 
frequency drift 
over 
temperature 
(reference is 
30 °C)

MSI mode

T

J

 = –40 to 130 °C

-4

-

2

VDD(MSI)

(4)

MSI oscillator 
frequency drift 
over V

DD 

(reference is 3V)

MSI mode

MSI range 
0 to 3

1.58 

 V

DD

 

 3.6 V

-4

-

1

2.4 

 V

DD

 

 3.6 V

-1

-

1

MSI range 
4 to 7

1.58 

 V

DD

 

 3.6 V

-3

-

1

2.4 

 V

DD

 

 3.6 V

-1

-

1

MSI range 
8 to 11

1.58 

 V

DD

 

 3.6 V

-3

-

1

2.4 

 V

DD

 

 3.6 V

-1

-

1

MSI range 
12 to 15

1.58 

 V

DD

 

 3.6 V

-3

-

1

2.4 

 V

DD

 

 3.6 V

-1

-

1

FSAMPLING
(MSI)

(3)(4)

MSI frequency 
variation in 
sampling mode 
(MSIBIAS = 1) 

MSI mode

T

J

 = –40 to 130 °C

-

-

0.2

CC 

jitter(MSI)

(3)

RMS 
cycle-to-cycle 
jitter

PLL mode

MSI range 0

-

60

-

ps

MSI range 4

-

160

-

MSI range 8

-

200

-

MSI range 12

-

1100

-

P jitter(MSI)

(3)

RMS period jitter PLL mode 

MSI range 0

-

40

-

MSI range 4

-

130

-

MSI range 8

-

170

-

MSI range 12

-

800

-

Table 82. MSI oscillator characteristics

(1)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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STM32U575xx

Electrical characteristics

305

t

su(MSI)

(3)

MSI oscillator 
startup time

(5)

MSI range 0 to 3

-

-

13 

MSIRC0 

cycles + 

11 MSI 

cycles

cyc

les

MSI range 4 to 7

-

-

MSIRC1 

cycles + 

11 MSI 

cycles

MSI range 8 to 11

-

-

MSIRC2 

cycles + 

11 MSI 

cycles

MSI range 12 to 15

-

-

MSIRC3 

cycles + 

11 MSI 

cycles

t

switch(MSI)

(3)

MSI oscillator 
transition time

(6)

-

-

-

destina-

tion MSI 

cycles

t

stab(MSI)

(3)

MSI oscillator 
stabilization time

Normal 
mode

Continuous 
mode

(7)

Final frequency

-

-

10

µs

Sampling 
mode

(8)

-

-

200

PLL mode, 
MSIPLL

 

FAST = 0

All MSI 
ranges

1% of final 
frequency

-

-

0.8

ms

PLL mode, 
MSIPLL

 

FAST = 1

All MSI ranges

2

cycles

I

DD(MSI_OFF

_PLLFAST)

(3)

MSI PLL-mode 
oscillator power 
consumption 
when MSI is 
disabled with 
PLL accuracy 
retention

MSIPLL

 

EN = 1 and 
MSIPLL

 

FAST = 1

LDO

MSI range 0 to 3

-

6.6

-

µA

MSI range 4 to 7

-

1.6

-

MSI range 8 to 11

-

1.4

-

MSI range 12 to 15

-

0.8

-

SMPS

MSI range 0 to 3

-

4.7

-

MSI range 4 to 7

-

1.4

-

MSI range 8 to 11

-

1.3

-

MSI range 12 to 15

-

0.8

-

Table 82. MSI oscillator characteristics

(1)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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220/346

DS13737 Rev 10

High-speed internal 48 MHz (HSI48) RC oscillator

          

I

DD(MSI)

(3)

MSI oscillator 
power 
consumption

Continuous 
mode

(7)

LDO

MSI range 0 to 3

-

21 + 2.5 
µA/MHz

-

µA

MSI range 4 to 15

-

19 + 2.5 
µA/MHz

-

SMPS

(9)

MSI range 0 to 3

-

21 + 1,3 
µA/MHz

-

MSI range 4 to 15

-

19 + 1,3 
µA/MHz

-

Sampling 
mode

(8)

LDO

Range 0 to 3

-

3 + 2.5 

µA/MHz

-

Range 4 to 15

-

1 + 

2.5µA/

MHz

-

SMPS

Range 0 to 3

-

3 + 1 

µA/MHz

-

Range 4 to 15

-

1 + 1 

µA/MHz

-

1. Evaluated by characterization and not tested in production, unless otherwise specified.

2. In PLL mode, the MSI accuracy is the LSE crystal accuracy.

3. Specified by design. Not tested in production.

4. This is a deviation for an individual part once the initial frequency has been measured.

5. The MSI startup time is the time when the four MSIRCs are in power down.

6. This delay is the time to switch from one MSIRC to another one. In case the destination MSIRC is in power down, the total 

delay is t

su(MSI) 

+ t

switch(MSI)

.

7. The MSI is in continuous mode when the internal regulator is in voltage range 1, 2 or 3.

8. The MSI is in sampling mode when MSIBIAS = 1 in RCC_ICSCR1, and the regulator is in voltage range 4, or when the 

device is in Stop 1 or Stop 2 mode.

9. SMPS efficiency in range 1, based on V

CORE

 current = 19.4 mA.

Table 82. MSI oscillator characteristics

(1)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 83. HSI48 oscillator characteristics 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f

HSI48

HSI48 frequency after factory calibration V

DD 

= 3.0 V, T

= 30 °C

47.5

48

48.5

MHz

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221/346

STM32U575xx

Electrical characteristics

305

Figure 35. HSI48 frequency versus temperature

TRIM

HSI48

(1)

User trimming step

-

-

0.12

0.18

%

USER TRIM 

COVERAGE

(2)

User trimming coverage

±63 steps

±4.5

±7.56

-

DuCy

HSI48

(1)

Duty cycle

-

45

-

55

ACC

HSI48_REL

(2)

Accuracy of the HSI48 oscillator over 
temperature (factory calibrated)

 

Reference is 3 V and 30 °C

(3)

.

1.58 V 

 V

DD

 

 3.6 V,

 

T

J

 = –40 to 125 °C

-3

-

2

VDD(HSI48)

(1)

HSI48 frequency drift with V

DD

(4)

3.0 V 

 V

DD

 

 3.6 V

-

0.025

0.05

1.58 V 

 V

DD

 

 3.6 V

-

0.05

0.1

N

T

 jitter

(1)

Next transition jitter

 

Accumulated jitter on 28 cycles

(5)

-

-

±0.15

-

ns

P

T

 jitter

(1)

Paired transition jitter

 

Accumulated jitter on 56 cycles

(5)

-

-

±0.25

-

t

su(HSI48)

(1)

HSI48 oscillator startup time

-

-

2.5

6

μ

s

I

DD(HSI48)

(1)

HSI48 oscillator power consumption

-

-

350

400

μ

A

1. Specified by design. Not tested in production.

2. Evaluated by characterization. Not tested in production.

3.

f

HSI

 = ACC

HSI48_REL

 + 

V

DD

.

4. These values are obtained with one of the following formula: (Freq(3.6 V) - Freq(3.0 V))  / Freq(3.0 V) or 

(Freq(3.6 V) - Freq(1.58 V)) / Freq(1.58 V).

5. Jitter measurements are performed without clock source activated in parallel.

Table 83. HSI48 oscillator characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MSv69123V1

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Electrical characteristics

STM32U575xx

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DS13737 Rev 10

Low-speed internal (LSI) RC oscillator

          

5.3.10 PLL 

characteristics

The parameters given in the table below are derived from tests performed under 
temperature and V

DD

 supply voltage conditions summarized in 

Table 32

.

          

Table 84. LSI oscillator characteristics 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f

LSI

LSI frequency

V

DD

 = 3.0 V, T

J

 = 30 °C, LSIPREDIV = 0

31.4

-

32.6

kHz

V

DD

 = 3.0 V, T

J

 = 30 °C, LSIPREDIV = 1

0.245

-

0.255

1.58 V

 V

DD

 

 3.6 V, T

J

 = –40 to 125 °C

30.4

(1)

-

33.6

(1)

DuCy

LSI

LSI duty cycle

LSIPREDIV = 1

-

50

-

%

t

SU(LSI)

(2)

LSI oscillator startup time

-

-

230

260

μ

s

t

STAB(LSI)

(2)

LSI oscillator stabilization time  5% of final frequency

-

230

260

I

DD(LSI)

(2)

LSI oscillator power 
consumption

LSIPREDIV = 0

-

140

255

nA

LSIPREDIV = 1

-

130

240

1. Evaluated by characterization. Not tested in production.

2. Specified by design. Not tested in production.

Table 85. PLL characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f

PLL_IN

PLL input clock

-

4

-

16

MHz

PLL input clock 
duty cycle

-

10

-

90

%

f

PLL_OUT

PLL P, Q, R 
output clock

Voltage scaling range 1

1

-

160

(2)

MHz

Voltage scaling range 2

1

-

110

Voltage scaling range 3

1

-

55

f

VCO_OUT

PLL VCO output

Voltage scaling range 1, 2

128

-

544

Voltage scaling range 3

128

-

330

Duty cycle with division 1

40

-

60

%

t

LOCK

(3)(4)

PLL lock time

Integer mode

-

25

50

μ

s

Fractional mode

-

40

65

Jitter

RMS cycle-to-
cycle jitter

Integer mode, VCO = 544 MHz

-

20

-

±ps

Fractional mode, VCO = 544 MHz

-

70

-

RMS period jitter

Integer mode, VCO = 544 MHz

-

35

-

Fractional mode, VCO = 544 MHz

-

45

-

Long-term 
jitter

(5)

f

PLL_IN

 = 8 MHz

Integer mode, VCO = 544 MHz

-

160

-

Fractional mode, VCO = 544 MHz

-

170

-

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STM32U575xx

Electrical characteristics

305

5.3.11 Flash 

memory 

characteristics

          

I

DD(PLL)

PLL power 
consumption on 
V

DD

with LDO

VCO freq = 160 MHz, 
1 clock output

Range 1

-

370

-

μ

A

VCO freq = 160 MHz, 
3 clock outputs

Range 1

-

390

-

VCO freq = 200 MHz, 
1 clock output

Range 1

-

460

-

Range 2

-

435

-

Range 3

-

410

-

VCO freq = 336 MHz, 
1 clock output

Range 1

-

710

-

VCO freq = 544 MHz, 
1 clock output

Range 1

-

1100

-

I

DD(PLL)

PLL power 
consumption on 
V

DD

with SMPS

VCO freq = 160 MHz, 
1 clock output

Range 1, I

VCORE

(6)

 = 19.4 mA

-

260

-

VCO freq = 160 MHz, 
3 clock outputs

Range 1, I

VCORE

(6)

 = 19.4 mA

-

270

-

VCO freq = 200 MHz, 
1 clock output

Range 1, I

VCORE

(6)

 = 19.4 mA

-

320

-

Range 2, I

VCORE

(6)

 = 11.7 mA

-

300

-

Range 3, I

VCORE

(6)

 = 5.74 mA

-

290

-

VCO freq = 336 MHz, 
1 clock output

Range 1, I

VCORE

(6)

 = 19.4 mA

-

470

-

VCO freq = 544 MHz, 
1 clock output

Range 1, I

VCORE

(6)

 = 19.4 mA

-

730

-

1. Specified by design and not tested in production, unless otherwise specified.

2. PLL1 output Q and PLL2 output Q can be up to 200 MHz only when selected as OCTOSPI clock.

3. Evaluated by characterization. Not tested in production.

4. Lock time is the duration until PLLxRDY flag (2% of final frequency).

5. Measured on 5000 cycles.

6. SMPS efficiency based on CoreMark RUN current on V

CORE

 at max frequency of each voltage range. 

Table 85. PLL characteristics

(1)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 86. Flash memory characteristics

(1)

 

Symbol

Parameter

 Conditions

Typ

Max

(2)

Unit

t

prog

128-bit programming time

Normal mode

118

118

µs

Burst mode

48

48

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STM32U575xx

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DS13737 Rev 10

          

t

prog_page

One 8-Kbyte page programming time

f

AHB

 = 160 MHz, normal mode

60.2

-

ms

f

AHB

 = 160 MHz, burst mode

24.5

-

t

prog_bank

One 1-Mbyte bank programming time

f

AHB

 = 160 MHz, normal mode

7710

-

f

AHB

 = 160 MHz, burst mode

3140

-

t

ERASE

One 8-Kbyte page erase time

10 k endurance cycles

1.5

2.4

100 k endurance cycles

1.7

3.4

t

ME

Mass erase time (one bank)

10 k endurance cycles

195

308

Mass erase time (two banks)

390

616

I

DD

(3)

Average consumption from V

DD

Write mode 

2.1

-

mA

Erase mode 

1.3

-

Maximum current (peak)

Write mode 

2.6

-

Erase mode 

3.0

-

1. Specified by design. Not tested in production.

2. Evaluated by characterization after cycling. Not tested in production.

3. Evaluated by characterization. Not tested in production.

Table 86. Flash memory characteristics

(1)

 (continued)

Symbol

Parameter

 Conditions

Typ

Max

(2)

Unit

Table 87. Flash memory endurance and data retention 

Symbol

Parameter

 Conditions

Min

(1)

Unit

N

END

Endurance

Whole bank

T

A

 = –40 to 125 °C

10

kcycles

Limited to 256 Kbytes per bank

100

t

RET

Data retention

Whole bank

T

A

 = 85 °C after 1 kcycle

(2)

30

Years

T

A

 = 105 °C after 1 kcycle

(2)

15

T

A

 = 125 °C after 1 kcycle

(2)

10

T

A

 = 55 °C after 10 kcycles

(2)

30

T

A

 = 85 °C after 10 kcycles

(2)

15

T

A

 = 105 °C after 10 kcycles

(2)

10

Limited to 256 Kbytes per bank

T

A

 = 55 °C after 100 kcycles

(2)

30

T

A

 = 85 °C after 100 kcycles

(2)

15

T

A

 = 105 °C after 100 kcycles

(2)

10

1. Evaluated by characterization. Not tested in production.

2. Cycling performed over the whole temperature range.

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5.3.12 EMC 

characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling two LEDs through the 
I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The 
failure is indicated by the LEDs as follows:

Electrostatic discharge (ESD) (positive and negative): applied to all device pins until a 
functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

FTB (fast transient voltage burst) (positive and negative): applied to VDD and VSS pins 
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant 
with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. 

The test results are given in the table below. They are based on the EMS levels and classes 
defined in application note 

EMC design guide for STM8, STM32 and Legacy MCUs 

(

AN1709).

          

Designing hardened software to avoid noise problems

The EMC characterization and optimization are performed at component level with a typical 
application environment and simplified MCU software. Note that good EMC performance is 
highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and 
prequalification tests in relation with the EMC level requested for the application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

Corrupted program counter

Unexpected reset

Critical data corruption (control registers)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be 
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 
1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of 
specification values. When unexpected behavior is detected, the software can be hardened 

Table 88. EMS characteristics 

Symbol

Parameter

Conditions

Level/

Class

V

FESD

Voltage limits to be applied on any I/O pin to 
induce a functional disturbance

V

DD

 = 3.3 V, T

A

 = +25 °C, f

HCLK

 = 160 MHz, 

BGA169 conforming to IEC 61000-4-2

3B

V

EFTB

Fast transient voltage burst limits to be 
applied through 100 pF on V

DD

 and V

SS 

pins 

to induce a functional disturbance

V

DD

 = 3.3 V, T

A

 = +25 °C, f

HCLK

 = 160 MHz, 

BGA169 conforming to IEC 61000-4-4

5A

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to prevent unrecoverable errors occurring. See application note 

Software techniques for 

improving microcontrollers EMC performance

 (AN1015) for more details.

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is 
executed (toggling two LEDs through the I/O ports). This emission test is compliant with 
IEC 61967-2 standard that specifies the test board and the pin loading.

           

5.3.13 Electrical 

sensitivity characteristics

Based on three different tests (ESD, latch-up) using specific measurement methods, the 
device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are 
applied to the pins of each sample according to each pin combination. The sample size 
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test 
conforms to the ANSI/JEDEC standard.

           

Table 89. EMI characteristics for 

f

HSE

 = 8 MHz and 

f

HCLK

 = 160 MHz 

Symbol Parameter

Conditions

Monitored frequency 

band

Value

Unit

S

EMI

Peak

(1)

V

DD 

= 3.6 V, T

A = 

25 °C, 

BGA169 package compliant 

with IEC 61967-2

0.1 MHz to 30 MHz

5

dB

μ

V

30 MHz to 130 MHz

6

130 MHz to 1 GHz

6

1 GHz to 2 GHz

7

Level

(2)

0.1 MHz to 2 GHz

2

-

1. Refer to the EMI radiated test section of the application note 

EMC design guide for STM8, STM32 and Legacy MCUs

 

(AN1709).

2. Refer to the EMI level classification section of the application note 

EMC design guide for STM8, STM32 and Legacy MCUs

 

(AN1709).

Table 90. ESD absolute maximum ratings

(1)

 

Symbol

Ratings

Conditions

Packages

Class

Max 

value

Unit

V

ESD(HBM)

Electrostatic discharge 
voltage (human body model)

T

A

 = 25 °C, conforming to 

ANSI/ESDA/JEDEC JS-001

All

2

2000

V

V

ESD(CDM)

Electrostatic discharge 
voltage (charge device model)

T

A

 = 25 °C, conforming to 

ANSI/ESDA/JEDEC JS-002

LQFP100
LQFP144

C1

250

UFQFPN48

LQFP48
LQFP64

C2a

500

WLCSP90

UFBGA132
UFBGA169

C2b

750

1. Evaluated by characterization. Not tested in production.

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Static latch-up

The following complementary static tests are required on three parts to assess the latch-up 
performance: 

A supply overvoltage is applied to each power supply pin.

A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78E IC latch-up standard.

          

5.3.14 I/O 

current 

injection characteristics

As a general rule, the current injection to the I/O pins, due to external voltage below V

SS

 or 

above V

DDIOx

 (for standard, 3.3 V-capable I/O pins) must be avoided during normal product 

operation. However, in order to give an indication of the robustness of the microcontroller if 
abnormal injection accidentally happens, some susceptibility tests are performed on a 
sample basis during the device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting 
current into the I/O pins programmed in floating-input mode. While this current is injected 
into the I/O pin, one at a time, the device is checked for functional failures. 

The failure is indicated by an out-of-range parameter, such as an ADC error above a certain 
limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on 
adjacent pins (out of the -5 µA/+0 µA range), or other functional failure (for example reset 
occurrence or oscillator frequency deviation).

The characterization results are given in the table below. The negative induced leakage 
current is caused by the negative injection. The positive induced leakage current is caused 
by the positive injection.

          

Table 91. Electrical sensitivities

(1)

 

Symbol

Parameter

Conditions

Class

LU

Static latch-up class

T

J

 = 130 °C conforming to JESD78E

2

1. Evaluated by characterization. Not tested in production.

Table 92. I/O current injection susceptibility

(1)(2)

 

Symbol

Description

Functional susceptibility

Unit

Negative injection

Positive injection

I

INJ

Injected current on OPAMP1_VINM, 
OPAMP2_VINM, PA4, PA5, PB0, PE7, PB15, 
PC11, and PD0 pins

0

0

mA

Injected current on all other pins

5

N/A

1. Evaluated by characterization. Not tested in production.

2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For 

instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

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5.3.15 I/O 

port 

characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests 
performed under the conditions summarized in 

Table 32

. All I/Os are designed as 

CMOS- and TTL-compliant.

Note:

For information on GPIO configuration, refer to the application note ‘STM32 GPIO 
configuration for hardware settings and low-power consumption’ (AN4899).

          

Table 93. I/O static characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

IL

(2)

I/O input 
low-level 
voltage

1.08 V 

 V

DDIOx 

 3.6 V

-

-

0.3 V

DDIOx

V

All I/Os except FT_c

-

-

0.38 V

DDIOx

(3)

FT_c I/Os

-

-

0.3 V

DDIOx

V

IH

(2)

I/O input 
high-level 
voltage

1.08 V 

 V

DDIOx 

 3.6 V

0.7 V

DDIOx 

-

-

All I/Os except FT_c

0.5 V

DDIOx

 

+ 0.2

(3)

-

-

FT_c I/Os

0.7 V

DDIOx 

-

-

V

hys

(3)

Input 
hysteresis

TT_xx, FT_xx I/Os

-

250

-

mV

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I

lkg

(3)(4)

Input 
leakage 
current

All I/Os except FT_u, 
FT_c, FT_d, FT_o, 
FT_t, TT_xx

V

IN

 

 Max (V

DDXXX

)

(5)

-

-

150

nA

Max (V

DDXXX

) < V

IN

 

 Max (V

DDXXX

) + 1 V

(6)

-

-

2000

Max (V

DDXXX

) + 1 V < V

IN

 

 5.5 V

(6)

-

-

500

FT_o I/Os
Rev. X

V

IN

 

 Max (V

DDXXX

)

(5)

-

-

150

Max (V

DDXXX

) < V

IN

 

 Max (V

DDXXX

) + 1 V

(6)

-

-

2000

Max (V

DDXXX

) + 1 V < V

IN

 

 5.5 V

(6)

-

-

500

FT_o I/Os
Other revisions

V

IN

 

 Max (V

DDXXX

)

(5)

-

-

50

Max (V

DDXXX

) < V

IN

 

 Max (V

DDXXX

) + 1 V

(6)

-

-

500

Max (V

DDXXX

) + 1 V < V

IN

 

 5.5 V

(6)

-

-

200

FT_u I/Os

V

IN

 

 Max (V

DDXXX

)

(5)

-

-

200

Max (V

DDXXX

) < V

IN

 

 Max (V

DDXXX

) + 1 V

(6)

-

-

2500

Max (V

DDXXX

) + 1 V < V

IN

 

 5.5 V

(6)

-

-

500

FT_c I/Os

V

IN

 

 Max (V

DDXXX

)

-

-

1500

Max (V

DDXXX

) < V

IN

 

 5 V

(6)

-

-

2000

FT_d I/Os

V

IN

 

 Max (V

DDXXX

)

-

-

1500

Max (V

DDXXX

) < V

IN

 

 5.5 V

(6)

-

-

5000

FT_t I/Os

V

IN

 

 Max (V

DDXXX

)

-

-

300

Max (V

DDXXX

) < V

IN

 

 Max (V

DDXXX

) + 1 V

(6)

-

-

3000

Max (V

DDXXX

) + 1 V < V

IN

 

 5.5 V

(6)

-

-

600

Table 93. I/O static characteristics

(1)

 (continued)

Sy

mbol

Parameter

Conditions

Min

Typ

Max

Unit

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I

lkg

(3)(4)

Input 
leakage 
current

TT_xx I/Os except 
OPAMPx_VINM 
(x = 1, 2) 

V

IN

 

 Max (V

DDXXX

)

-

-

500

nA

OPAMPx_VINM (x = 1, 2) dedicated input leakage 
current

-

-

(7)

R

PU

Weak 
pull-up 
equivalent 

-

30

40

50

k

R

PD

Weak 
pull-down 
equivalent 

-

30

40

50

C

IO

I/O pin 
capacitance

-

-

5

-

pF

1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For 

instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

2. Refer to 

Figure 36: I/O input characteristics (all I/Os except BOOT0 and FT_c)

.

3. Specified by design. Not tested in production.

4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following 

formula: I

Total_Ileak_max

 = 10 

μ

A+ [number of I/Os where V

IN

 is applied on the pad] 

 I

lkg

 max.

5. Max (V

DDXXX

) is the maximum value of all the I/O supplies. The I/O supplies depend on the I/O structure options, as 

described in 

Table 25: Legend/abbreviations used in the pinout table

.

6. To sustain a voltage higher than Min (V

DD

, V

DDA

, V

DDUSB

, V

DDIO2

) +0.3 V, the internal pull-up and pull-down resistors must 

be disabled.

7. Refer to I

bias

 in the OPAMP characteristics table for the values of the OPAMP dedicated input leakage current.

8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. 

This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

Table 93. I/O static characteristics

(1)

 (continued)

Sy

mbol

Parameter

Conditions

Min

Typ

Max

Unit

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All I/Os are CMOS- and TTL-compliant (no software configuration required). Their 
characteristics cover more than the strict CMOS-technology or TTL parameters. The 
coverage of these requirements is shown in the figure below.

Figure 36. I/O input characteristics (all I/Os except BOOT0 and FT_c)

Output driving current

The GPIOs (except PC13, PC14, PC15) can sink or source up to ±8 mA, and sink or source 
up to ± 20 mA (with a relaxed V

OL

/V

OH

). PC13, PC14, PC15 are limited in source capability: 

+3 mA shared between the three I/Os. These GPIOs have the same sink capability than 
other GPIOs.

In the user application, the number of I/O pins tat can drive current must be limited to 
respect the absolute maximum rating specified in 

Section 5.2: Absolute maximum ratings

:

The sum of the currents sourced by all the I/Os on V

DDIOx

, plus the maximum 

consumption of the MCU sourced on V

DD

, cannot exceed the absolute maximum rating 

Σ

I

VDD

 (see 

Table 30: Current characteristics

).

The sum of the currents sunk by all the I/Os on V

SS

, plus the maximum consumption of 

the MCU sunk on V

SS

, cannot exceed the absolute maximum rating 

Σ

I

VSS

 

(see 

Table 30: Current characteristics

). 

MSv69136V1

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Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests 
performed under the ambient temperature and supply voltage conditions summarized in 

Table 32

All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified).

          

          

Table 94. Output voltage characteristics (all I/Os except FT_t I/Os in V

BAT

 mode,

and FT_o I/Os

(1)

)

(2)(3)

 

Symbol

Parameter

Conditions

Min

Max

Unit

V

OL

Output low-level voltage

CMOS port

(4)

, |I

IO

|

 

= 8 mA, 

2.7 V 

 V

DDIOx

 

 3.6 V

-

0.4

V

V

OH

Output high-level voltage

V

DDIOx 

- 0.4

-

V

OL

(5)

Output low-level voltage

TTL port

(4)

,|I

IO

|

 

= 8 mA, 

 

2.7 V 

 V

DDIOx

 

 3.6 V

-

0.4

V

OH

(5)

Output high-level voltage

2.4

-

V

OL

(5)

Output low-level voltage

All I/Os, |I

IO

|

 

= 20 mA,

 

2.7 V 

 V

DDIOx

 

 3.6 V

-

1.3

V

OH

(5)

Output high-level voltage

V

DDIOx 

- 1.3

-

V

OL

(5)

Output low-level voltage

|I

IO

| = 4 mA,

 

1.58 V 

 V

DDIOx 

 3.6 V

-

0.4

V

OH

(5)

Output high-level voltage

V

DDIOx 

- 0.4

-

V

OL

(5)

Output low-level voltage

|I

IO

| = 1 mA,

 

1.08 V 

 V

DDIOx 

<3.6 V

-

0.4

V

OH

(5)

Output high-level voltage

V

DDIOx 

- 0.4

-

V

OLFM+

(5)

Output low-level voltage for 
a FT_f I/O pin in FM+ mode

|I

IO

|

 

= 20 mA, 

 

2.7 V 

 V

DDIOx

 

 3.6 V

-

0.4

|I

IO

|

 

= 10 mA,

 

1.58 V 

 V

DDIOx 

 3.6 V

-

0.4

|I

IO

|

 

= 2 mA,

 

1.08 V 

 V

DDIOx 

< 3.6 V

-

0.4

1. FT_t I/O characteristics are degraded only in V

BAT

 mode (refer to 

Table 95

). FT_o I/O characteristics are provided in this 

table for revision X devices. FT_o I/O characteristics are provided in 

Table 95

 for all other device revisions.

2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For 

instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

3. The I

IO

 current sourced or sunk by the device must always respect the absolute maximum rating specified in 

Table 30: 

Current characteristics

and the sum of

 

the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always 

respect the absolute maximum ratings 

Σ

I

IO

.

4. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

5. Specified by design. Not tested in production.

Table 95. Output voltage characteristics for FT_t I/Os in V

BAT

 mode, and for FT_o I/Os

(1)

 

(2)

 

Symbol

Parameter

Conditions

Min

Max

Unit

V

OL

Output low-level voltage

|I

IO

|

 

= 0.5 mA, 2.7 V 

 V

SW

 

 3.6 V

-

0.4

V

V

OH

Output high-level voltage

V

SW 

- 0.4

-

V

OL

Output low-level voltage

|I

IO

|

 

= 0.25 mA, 1.58 V 

 V

SW

 

 3.6 V

-

0.4

V

OH

Output high-level voltage

V

SW 

- 0.4

-

1. Specified by design. Not tested in production.

2. FT_o I/Os output voltage characteristics are provided in 

Table 94

 for revision X devices.

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Output AC characteristics

The definition and values of output AC characteristics are given in 

Figure 37: Output AC 

characteristics definition

 and in the table below respectively.

Unless otherwise specified, the parameters given are derived from tests performed under 
the ambient temperature and supply voltage conditions summarized in 

Table 32

.

          

Table 96. Output AC characteristics, HSLV OFF (all I/Os except FT_c,

FT_t in V

BAT

 mode and FT_o I/Os

(1)

)

(2)(3)(4)

 

Speed Symbol

Parameter

Conditions

Min

Max

Unit

00

Fmax

Maximum frequency
all I/Os

C

L

 = 50 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

12.5

MHz

C

L

 = 50 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

5

C

L

 = 50 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

1

C

L

 = 10 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

12.5

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

5

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

1

t

r

/t

f

Output rise and fall time
all I/Os

C

L

 = 50 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

17

ns

C

L

 = 50 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

33

C

L

 = 50 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

85

C

L

 = 10 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

12.5

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

25

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

50

01

Fmax

Maximum frequency
all I/Os

C

L

 = 30 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

55

MHz

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

12.5

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

2.5

C

L

 = 10 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

55

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

12.5

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 

<1.58 V

-

2.5

t

r

/t

f

Output rise and fall time
all I/Os

C

L

 = 30 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

5.8

ns

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

10

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

18

C

L

 = 10 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

4.2

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

7.5

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

12

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Electrical characteristics

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DS13737 Rev 10

10

Fmax

Maximum frequency
all I/Os

C

L

 = 30 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

100

(5)

MHz

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

33

(5)

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

5

C

L

 = 10 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

133

(5)

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

40

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

5

t

r

/t

f

Output rise and fall time
all I/Os

C

L

 = 30 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

3.3

(5)

ns

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

6.0

(5)

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

13.3

C

L

 = 10 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

2

(5)

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

4.1

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

9.2

11

Fmax

Maximum frequency
All I/Os except FT_c, FT_v, 
and TT_v

C

L

 = 30 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

100

(5)

MHz

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

33

(5)

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

5

C

L

 = 10 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

133

(5)

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

40

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

5

Maximum frequency
FT_v and TT_v I/Os

C

L

 = 30 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

140

(5)

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

40

(5)

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

5

C

L

 = 10 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

166

(5)

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

50

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

5

t

r

/t

f

Output rise and fall time
All I/Os except FT_c, FT_v, 
and TT_v

C

L

 = 30 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

3.3

(5)

ns

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

6.0

(5)

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

13.3

C

L

 = 10 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

2.0

(5)

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

4.1

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

9.2

Table 96. Output AC characteristics, HSLV OFF (all I/Os except FT_c,

FT_t in V

BAT

 mode and FT_o I/Os

(1)

)

(2)(3)(4)

 (continued)

Speed Symbol

Parameter

Conditions

Min

Max

Unit

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STM32U575xx

Electrical characteristics

305

          

11 

(cont’d)

t

r

/t

f

Output rise and fall time
FT_v and TT_v I/Os

C

L

 = 30 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

2.5

(5)

ns

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

5.0

(5)

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

11

C

L

 = 10 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

1.66

(5)

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

3.1

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

7

Fm+

Fmax

Maximum frequency

C

L

 = 550 pF, 1.08 V 

 V

DDIOx

 < 3.6 V

-

1

MHz

t

f

Output fall time

(6)

C

L

 = 100 pF, 1.58 V 

 V

DDIOx

 < 3.6 V

-

50

ns

C

L

 = 100 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

80

C

L

 = 550 pF, 1.58 V 

 V

DDIOx

 < 3.6 V

-

100

C

L

 = 550 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

220

1. FT_t I/O characteristics are degraded only in V

BAT

 mode (refer to 

Table 99

). FT_o I/O characteristics are provided in this 

table for revision X devices. FT_o I/O characteristics are provided in 

Table 99

 for all other device revisions.

2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For 

instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

3. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO 

port configuration register.

4. Specified by design. Not tested in production.

5. Compensation system enabled.

6. The fall time is defined between 70% and 30% of the output waveform accordingly to I

2

C specification.

Table 96. Output AC characteristics, HSLV OFF (all I/Os except FT_c,

FT_t in V

BAT

 mode and FT_o I/Os

(1)

)

(2)(3)(4)

 (continued)

Speed Symbol

Parameter

Conditions

Min

Max

Unit

Table 97. Output AC characteristics, HSLV ON (all I/Os except FT_c)

(1)(2)(3)(4)

 

Speed Symbol

Parameter

Conditions

Min

Max

Unit

00

Fmax

Maximum frequency

C

L

 = 50 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

10

MHz

C

L

 = 50 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

4

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

15

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

4

t

r

/t

f

Output rise and fall time

C

L

 = 50 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

18

ns

C

L

 = 50 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

32

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

12

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

21

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DS13737 Rev 10

01

Fmax

Maximum frequency

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

50

MHz

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

10

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

67

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

10

t

r

/t

f

Output rise and fall time

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

5.3

ns

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

10.6

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

3.1

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

5.6

10

Fmax

Maximum frequency

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

75

(5)

MHz

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

15

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

100

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

15

t

r

/t

f

Output rise and fall time

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

4.4

(5)

ns

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

9.6

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

2.2

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

4.7

11

Fmax

Maximum frequency
All I/Os except FT_c, FT_v, 
and TT_v

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

75

(5)

MHz

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

15

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

100

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

15

Maximum frequency
FT_v and TT_v I/Os

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

110

(5)

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

25

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

150

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

25

11

t

r

/t

f

Output rise and fall time
All I/Os except FT_c, FT_v, 
and TT_v

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

4.4

(5)

ns

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

9.6

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

2.2

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

4.7

Output rise and fall time
FT_v and TT_v I/Os

C

L

 = 30 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

3.0

(5)

C

L

 = 30 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

6.6

C

L

 = 10 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

1.6

(5)

C

L

 = 10 pF, 1.08 V 

 V

DDIOx

 < 1.58 V

-

3.4

1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For 

instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of 

GPIO port configuration register.

Table 97. Output AC characteristics, HSLV ON (all I/Os except FT_c)

(1)(2)(3)(4)

 (continued)

Speed Symbol

Parameter

Conditions

Min

Max

Unit

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STM32U575xx

Electrical characteristics

305

          

          

3. Specified by design. Not tested in production.

4. FT_t I/O characteristics are degraded only in V

BAT

 mode (refer to 

Table 99

).

5. Compensation system enabled.

Table 98. Output AC characteristics for FT_c I/Os

(1)(2)

 

Speed Symbol

Parameter

Conditions

Min

Max

Unit

00

Fmax

Maximum frequency

All I/Os, C

L

 = 50 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

10

MHz

All I/Os, C

L

 = 50 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

5

t

r

/t

f

Output rise and fall time

All I/Os, C

L

 = 50 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

33

ns

All I/Os, C

L

 = 50 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

66

01

Fmax

Maximum frequency

All I/Os, C

L

 = 50 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

25

MHz

All I/Os, C

L

 = 50 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

10

t

r

/t

f

Output rise and fall time

All I/Os, C

L

 = 50 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

13

ns

All I/Os, C

L

 = 50 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

33

1x

Fmax

Maximum frequency

All I/Os, C

L

 = 50 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

40

MHz

All I/Os, C

L

 = 50 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

20

t

r

/t

f

Output rise and fall time

All I/Os, C

L

 = 50 pF, 2.7 V 

 V

DDIOx

 

 3.6 V

-

8

ns

All I/Os, C

L

 = 50 pF, 1.58 V 

 V

DDIOx

 < 2.7 V

-

17

1. Specified by design. Not tested in production.

2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of 

GPIO port configuration register.

Table 99. Output AC characteristics for FT_t I/Os in V

BAT

 mode, and for FT_o I/Os

(1)(2)

 

Symbol

Parameter

Conditions

Min

Max

Unit

Fmax

Maximum frequency

C

L

 = 50 pF, 2.7 V 

 V

SW

 

 3.6 V

-

0.5

MHz

C

L

 = 50 pF, 1.58 V 

 V

SW

 < 2.7 V

-

0.25

t

r

/t

f

Output rise and fall time

C

L

 = 50 pF, 2.7 V 

 V

SW

 

 3.6 V

-

400

ns

C

L

 = 50 pF, 1.58 V 

 V

SW

 < 2.7 V

-

900

1. Specified by design. Not tested in production.

2. FT_o I/Os output AC characteristics are provided in 

Table 96

 for revision X devices.

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STM32U575xx

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DS13737 Rev 10

Figure 37. Output AC characteristics definition

5.3.16 NRST 

pin 

characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent 
pull-up resistor, R

PU

.

Unless otherwise specified, the parameters given in the table below are derived from tests 
performed under the ambient temperature and supply voltage conditions summarized 
in 

Table 32

.

          

Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the 

specified capacitance.  

T

10%

50%

90%

10%

50%

90%

r(IO)out

t

f(IO)out

t

Table 100. NRST pin characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

IL(NRST)

NRST input low-level voltage

-

-

-

0.3 x V

DD

V

V

IH(NRST)

NRST input high-level voltage

-

0.7 x V

DD

-

-

V

hys(NRST)

NRST Schmitt trigger voltage 
hysteresis 

-

-

200

-

mV

R

PU

Weak pull-up equivalent resistor

(2)

V

IN

 = V

SS

30

40

50

k

t

F(NRST)

NRST input filtered pulse

-

-

-

50

ns

t

NF(NRST)

NRST input not-filtered pulse

1.71 V 

 V

DD

 

 3.6 V

330

-

-

1.58 V 

 V

DD

 

 3.6 V

1000

-

-

1.  Specified by design. Not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series 

resistance is minimal (~10% order)

.

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Figure 38. Recommended NRST pin protection 

1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

 max level specified in the above table. 

Otherwise the reset is not taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

5.3.17 

Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is 
detected by the event controller.

5.3.18 

Analog switches booster

          

MS19878V3

R

PU

V

DD

Internal reset

External

reset circuit

(1)

NRST

(2)

Filter

0.1 μF

(3)

Table 101. EXTI input characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

PLEC

Pulse length to event controller

-

20

-

-

ns

1. Specified by design. Not tested in production.

Table 102. Analog switches booster characteristics

(1)

 

Symbol

Parameter

Min

Typ

Max

Unit

V

DD

Supply voltage

1.6

1.8

3.6

V

t

SU(BOOST)

Booster startup time

-

-

50

µs

I

DD(BOOST)

Booster consumption

-

-

125

µA

1. Specified by design. Not tested in production.

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DS13737 Rev 10

5.3.19 14-bit 

analog-to-digital 

converter (ADC1) characteristics

Unless otherwise specified, the parameters given in the table below are values derived from 
tests performed under ambient temperature, f

HCLK 

frequency and V

DDA

 supply voltage 

conditions summarized in 

Table 32

.

Note:

It is recommended to perform a calibration after each power-up.

          

Table 103. 14-bit ADC1 characteristics

(1)(2)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

DDA

Analog power supply for 
ADC ON

-

1.62

-

3.6

V

V

REF+

Positive reference 
voltage

V

DDA

 

 2 V

2

-

V

DDA

V

DDA

 < 2 V

V

DDA

V

REF-

Negative reference 
voltage

-

V

SSA

f

ADC

ADC clock frequency

1.62 V 

 V

DDA

 

 3.6 V

5

(3)

-

55

MHz

ADC clock ratio

-

45

-

55

%

f

s

Sampling rate

Resolution = 14 bits

0.23

-

2.5

Msps

Resolution = 12 bits

0.25

-

2.75

Resolution = 10 bits

0.28

-

3.05

Resolution = 8 bits

0.31

-

3.44

t

TRIG

External trigger period

Resolution = 14 bits

26

-

-

1/f

ADC

V

AIN

(4)

Conversion voltage 
range

-

0

-

V

REF+

V

V

CIMV

Common mode input 
voltage

-

V

REF+

/2 - 10% V

REF+

/2 V

REF+

/2 + 10%

V

R

AIN

(5)

External input 
impedance

Resolution = 14 bits 
T

= 130 °C

-

-

1000

Resolution = 12 bits 
T

= 130 °C

-

-

1000

Resolution = 10 bits 
T

= 130 °C

-

-

4700

Resolution = 8 bits 
T

= 130 °C

-

-

22000

C

ADC

Internal sample and 
hold capacitor

-

-

5

-

pF

t

ADCVREG_ 

STUP

ADC LDO startup time

-

-

-

17

µs

t

STAB

ADC power-up time

LDO already started

(3 × 1/f

ADC

) + 1 conversion

Cycle

t

CAL

Offset and linearity 
calibration time

-

31849

1/f

ADC

t

OFF_CAL

Offset calibration time

-

885

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305

t

LATR

Trigger conversion 
latency for regular and 
injected channels, 
without aborting the 
conversion

PRESC = 0

3

1/f

ADC

PRESC = 1

7

PRESC = 2

13

t

LATRINJ

Trigger conversion 
latency Injected 
channels aborting a 
regular conversion 

PRESC = 0

4

PRESC = 1

9

PRESC = 2

17

t

s

Sampling time

-

5

-

814

t

CONV

Total conversion time 
(including sampling 
time)

Resolution = N bits

t

s

 + N + 3

I

DDA_D(ADC)

ADC consumption on 
V

DDA

 Differential mode

f

s

 = 2.5 Msps,

 

resolution = 14 bits

-

970

-

µA

f

s

 = 1 Msps,

 

resolution = 14 bits

-

550

-

f

s

 = 10 ksps,

 

resolution = 14 bits

-

130

-

f

s

 = 2.5 Msps,

 

resolution = 12 bits

-

940

-

f

s

 = 2.5 Msps,

 

resolution = 10 bits

-

840

-

f

s

 = 2.5 Msps,

 

resolution = 8bits

-

730

-

I

DDV_D(ADC)

ADC consumption on 
V

REF+

 Differential mode

f

s

 = 2.5 Msps,

 

resolution = 14 bits

-

140

-

µA

f

s

 = 1 Msps,

 

resolution = 14 bits

-

80

-

f

s

 = 10 ksps,

 

resolution = 14 bits

-

13

-

f

s

 = 2.5 Msps,

 

resolution = 12 bits

-

140

-

f

s

 = 2.5 Msps,

 

resolution = 10 bits

-

140

-

f

s

 = 2.5 Msps,

 

resolution = 8bits

-

120

-

Table 103. 14-bit ADC1 characteristics

(1)(2)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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DS13737 Rev 10

The maximum value of R

AIN

 can be found in the table below.

          

I

DDA_s(ADC)

ADC consumption on 
V

DDA

 Singe-ended 

mode

f

s

 = 2.5 Msps,

 

resolution = 14 bits

-

980

-

µA

f

s

 = 1 Msps,

 

resolution = 14 bits

-

550

-

f

s

 = 10 ksps,

 

resolution = 14 bits

-

130

-

f

s

 = 2.5 Msps,

 

resolution = 12 bits

-

900

-

f

s

 = 2.5 Msps,

 

resolution = 10 bits

-

840

-

f

s

 = 2.5 Msps,

 

resolution = 8bits

-

770

-

I

DDV_s(ADC)

ADC consumption on 
V

REF+

 Single-ended 

mode

f

s

 = 2.5 Msps,

 

resolution = 14 bits

-

160

-

µA

f

s

 = 1 Msps,

 

resolution = 14 bits

-

90

-

f

s

 = 10 ksps,

 

resolution = 14 bits

-

15

-

f

s

 = 2.5 Msps,

 

resolution = 12 bits

-

150

-

f

s

 = 2.5 Msps,

 

resolution = 10 bits

-

150

-

f

s

 = 2.5 Msps,

 

resolution = 8bits

-

150

-

1. Specified by design. Not tested in production.

2. The voltage booster on the ADC switches must be used when V

DDA

 < 2.4 V (embedded I/O switches).

3. Degraded differential linearity error below 10 MHz.

4. Depending on the package, 

V

REF+

 can be internally connected to V

DDA

 and V

REF-

 can be internally connected to V

SSA

.

5. The maximum value of R

ain 

is specified to keep leakage induced offset within the specified tolerance. The tolerance is 

4 LSBs for 14-bit resolution and 2 LSBs for 12-bit, 10-bit, and 8-bit resolutions.

Table 103. 14-bit ADC1 characteristics

(1)(2)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 104. Maximum R

AIN

 for 14-bit ADC1

(1)(2)

 

(3)

 

Resolution

(4)

R

AIN

 max (

)

(5)

Sampling time [ns]

Sampling cycle at 5 MHz Sampling cycle at 55 MHz

14 bits

47

142

5

12

68

145

100

170

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305

12 bits

47

135

5

12

68

135

100

140

150

145

220

150

330

155

470

180

10 bits

47

128

5

12

68

130

100

132

150

134

220

140

330

146

470

160

680

176

12

1000

200

1500

240

20

2200

320

8 bits

47

123

5

12

68

124

100

125

150

128

220

130

330

137

470

140

680

157

1000

178

1500

204

2200

250

20

3300

313

4700

400

5

36

6800

546

10000

830

68

1. Specified by design. Not tested in production.
2. BOOSTEN and ANASWVDD configured properly according to V

DD

 and V

DDA

 values. 

3. Values without external capacitor.

Table 104. Maximum R

AIN

 for 14-bit ADC1

(1)(2)

 

(3)

 (continued)

Resolution

(4)

R

AIN

 max (

)

(5)

Sampling time [ns]

Sampling cycle at 5 MHz Sampling cycle at 55 MHz

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DS13737 Rev 10

          

4. The tolerance is 2 LSBs for 14 bits and 1 LSB for other resolutions.

5. The maximum value of R

AIN

 is obtained in a worst-case scenario: channel conversion in scan mode with channel i 

connected to V

REF+

 and channel i + 1 connected to V

REF-

.

Table 105. 14-bit ADC1 accuracy

(1)(2)

 

Symbol

Parameter

Conditions

(3)

Min

Typ

Max

Unit

ET

Total unadjusted error

Single ended

Rev. X

-

±25

-

LSB

Differential

-

±28

-

Single ended Other revision 

with extended 
calibration 
mode

-

±6

±12

Differential

-

±3

±6

EO

Offset error

Single ended

-

±6

±12

(4)

Differential

-

±2

±6

(4)

EG

Gain error

Single ended

Rev. X

-

±15

-

Differential

-

Single ended Other revision 

with extended 
calibration 
mode

-

±5

±10

Differential

-

±2.5

±5

ED

Differential linearity error

Single ended

f

ADC

 

 10 MHz

-

-0.9/+1.5

-0.9/+2.5

Differential

-

Single ended

f

ADC

 < 10 MHz

-

-0.9/+1.5

-1/+3

Differential

-

EL

Integral linearity error

Single ended

-

±3

±7

Differential

-

±2

±5

ENOB

Effective number of bits

Single ended

11

12

-

bits

Differential

11.8

12.8

-

SINAD

Signal-to-noise and 
distortion ratio

Single ended

68

74

-

dB

Differential

73

78

-

SNR

Signal-to-noise ratio

Single ended

68

74

-

Differential

73

78

-

THD

Total harmonic distortion

Single ended

-

-84

-80

Differential

-

-95

-89

1. Evaluated by characterization for BGA packages. Not tested in production. The values for LQFP packages may differ.

2. ADC DC accuracy values are measured after the internal calibration.

3. The I/O analog switch voltage booster is enable when V

DDA

 < 2.4 V (BOOSTEN = 1 in SYSCFG_CFGR1 when 

V

DDA

 < 2.4 V). The booster is disabled when V

DDA

 

 2.4 V. Resolution = 14 bits, no oversampling.

4. This parameter may degrade in case of digital activity on adjacent I/Os.

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305

Figure 39. ADC accuracy characteristics

Figure 40. Typical connection diagram when using the ADC

with FT/TT pins featuring analog switch function

1. Refer to the ADCx characteristic table for the values of R

AIN

 and C

ADC

.

2. C

parasitic

 represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance 

(refer to 

Table 93: I/O static characteristics

 for the value of the pad capacitance). A high C

parasitic

 value downgrades the 

conversion accuracy. To remedy this, f

ADC

 must be reduced.

3. Refer to 

Table 93: I/O static characteristics

 for the values of I

lkg

.

4. Refer to 

Section 5.1.6: Power supply scheme

.

General PCB design guidelines

The power-supply decoupling must be performed as shown in the corresponding 
power-supply scheme. The 100 nF capacitor must be ceramic (good quality) and must be 
placed as close as possible to the chip.

MSv19880V6

(1) Example of an actual transfer curve
(2) Ideal transfer curve
(3) End-point correlation line

n = ADC resolution
E

T

 = total unadjusted error: maximum deviation    

between the actual and ideal transfer curves

E

O

 = offset error: maximum deviation between the first 

actual transition and the first ideal one

E

G

 = gain error: deviation between the last ideal 

transition and the last actual one

E

D

 = differential linearity error: maximum deviation 

between actual steps and the ideal one

E

L

 = integral linearity error: maximum deviation between 

any actual transition and the end point correlation line

2

n

-1 

7

6

5

4

3

2
1

0

(1/2

n

)*V

REF+

Output code

E

O

V

SSA

2

n

-2 

2

n

-3 

V

REF+ 

(V

DDA

)

E

T

E

L

E

D

1 LSB ideal

E

G

(1)

(2)

(3)

(or                 )]

[1LSB =    

V

DDA

2

n

 

V

REF+

2

n

 

(2/2

n

)*V

REF+

(3/2

n

)*V

REF+

(4/2

n

)*V

REF+

(5/2

n

)*V

REF+

(6/2

n

)*V

REF+

(7/2

n

)*V

REF+

(2

n-3

/2

n

)*V

REF+

(2

n-2

/2

n

)*V

REF+

(2

n-1

/2

n

)*V

REF+

(2

n

/2

n

)*V

REF+

MSv67871V3

Sample-and-hold ADC converter

Converter

C

parasitic

(2)

I

lkg

(3)

 

C

ADC

V

DDA

(4)

R

AIN

(1)

V

AIN

R

ADC

V

REF+

(4)

V

SSA

I/O 

analog 

switch

Sampling 

switch with 

multiplexing

V

SS

V

SS

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DS13737 Rev 10

5.3.20 12-bit 

analog-to-digital 

converter (ADC4) characteristics

Unless otherwise specified, the parameters given in the table below are values derived from 
tests performed under ambient temperature, f

HCLK 

frequency and V

DDA

 supply voltage 

conditions summarized in 

Table 32

.

Note:

It is recommended to perform a calibration after each power-up.

          

Table 106. 12-bit ADC4 characteristics

(1)(2)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

DDA

Analog power supply for ADC 
ON

-

1.62

-

3.6

V

V

REF+

Positive reference voltage

-

1

-

V

DDA

V

REF-

Negative reference voltage

-

V

SSA

f

ADC

ADC clock frequency

1.62 V 

 V

DDA

 

 3.6 V

0.14

-

55

MHz

ADC clock duty cycle

-

45

-

55

%

f

s

Sampling rate

Resolution = 12 bits

0.01

-

2.75

Msps

Resolution = 10 bits

0.012

-

3.05

Resolution = 8 bits

0.014

-

3.43

Resolution = 6 bits

0.0175

-

3.92

t

TRIG

External trigger period

Resolution = 12 bits

16

-

-

1/f

ADC

V

AIN

(3)

Conversion voltage range

-

0

-

V

REF+

V

R

AIN

(4)

External input impedance
T

j

 = 130 °C

Resolution = 12 bits

-

-

2.2

k

Resolution = 10 bits

-

-

6.8

Resolution = 8 bits

-

-

33.0

Resolution = 6 bits

-

-

47.0

C

ADC

Internal sample and hold 
capacitor

-

-

5

-

pF

t

ADCVREG_ 

STUP

ADC LDO startup ready flag time

-

-

-

25

µs

t

STAB

ADC power-up time

LDO already started

(3 × 1/f

ADC

) + 1 conversion

Cycle

t

OFF_CAL

Offset calibration time

-

-

123

-

1/f

ADC

t

LATR

Trigger conversion latency

WAIT = 0, AUTOFF = 0, 
DPD = 0, f

ADC

 = HCLK

4

WAIT = 0, AUTOFF = 0, 
DPD = 0, f

ADC

 = HCLK/2

4

WAIT = 0, AUTOFF = 0, 
DPD = 0, f

ADC

 = HCLK/4

3.75

t

s

Sampling time

-

1.5

-

814.5

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t

CONV

Total conversion time (including 
sampling time)

Resolution = N bits, 
VREFPROTEN = 0

t

s

 + N + 0.5

1/f

ADC

Resolution = N bits, 
VREFPROTEN = 1
VREFSECSMP = 0

t

s

 + N + 0.5

-

t

s

 + N + 1.5

Resolution = N bits, 
VREFPROTEN = 1
VREFSECSMP = 1

t

s

 + N + 0.5

-

t

s

 + N + 2.5

I

DDA(ADC)

ADC consumption on V

DDA

f

s

 = 2.5 Msps

-

360

-

µA

f

s

 = 1 Msps

-

180

-

f

s

 = 10 ksps

-

10

-

AUTOFF = 1, DPD = 0, 
no conversion

-

9

-

AUTOFF = 1, DPD = 1, 
no conversion

-

0.1

-

I

DDV(ADC)

ADC consumption on V

REF+

f

s

 = 2.5 Msps

-

18

-

f

s

 = 1 Msps

-

10.2

-

f

s

 = 10 ksps

-

0.12

-

AUTOFF = 1, DPD = 0, 
no conversion

-

0.01

-

AUTOFF = 1, DPD = 1, 
no conversion

-

0.01

-

1. Specified by design. Not tested in production.

2. The voltage booster on the ADC switches must be used when V

DDA

 < 2.4 V (embedded I/O switches).

3. Depending on the package, 

V

REF+

 can be internally connected to V

DDA

 and V

REF-

 can be internally connected to V

SSA

.

4. The maximum value of R

ain 

is specified to keep leakage induced offset within the specified tolerance. The tolerance is 

2 LSBs.

Table 106. 12-bit ADC4 characteristics

(1)(2)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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DS13737 Rev 10

The maximum value of R

AIN

 can be found in the table below.

          

Table 107. Maximum R

AIN

 for 12-bit ADC4

(1)(2)(3)

 

Resolution

(4)

R

AIN

 max (

)

(5)

Sampling time [ns] Sampling cycle at 35 MHz Sampling cycle at 55 MHz

12 bits

47

276

12.5

19.5

68

288

100

306

150

336

220

377

19.5

39.5

330

442

470

526

680

650

39.5

1000

840

79.5

1500

1134

2200

1643

79.5

814.5

3300

2395

814.5

4700

3342

6800

4754

10000

6840

15000

9967

22000

14068

33000

19933

N/A

10 bits

47

86

3.5

7.5

68

90

100

95

150

108

7.5

220

116

330

136

470

161

12.5

680

212

1000

276

12.5

19.5

1500

376

19.5

39.5

2200

516

79.5

3300

735

39.5

4700

1012

6800

1423

79.5

814.5

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10 bits 

(cont’d)

10000

2040

814.5

814.5

15000

2978

22000

4356

33000

6443

47000

8925

8 bits

47

45

3.5

3.5

68

46

100

48

150

53

220

59

330

69

7.5

470

81

680

101

7.5

1000

130

1500

177

12.5

2200

242

12.5

19.5

3300

345

4700

475

19.5

39.5

6800

670

39.5

10000

963

79.5

15000

1417

79.5

22000

2040

814.5

33000

2995

814.5

47000

4158

6 bits

47

32

1.5

3.5

68

32

100

33

150

35

220

37

330

41

Table 107. Maximum R

AIN

 for 12-bit ADC4

(1)(2)(3)

 (continued)

Resolution

(4)

R

AIN

 max (

)

(5)

Sampling time [ns] Sampling cycle at 35 MHz Sampling cycle at 55 MHz

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DS13737 Rev 10

          

See 

Figure 39: ADC accuracy characteristics

Figure 40: Typical connection diagram when 

using the ADC with FT/TT pins featuring analog switch function

 and 

General PCB design 

guidelines

.

6 bits (cont’d)

470

49

3.5

3.5

680

61

1000

79

7.5

1500

106

7.5

2200

146

12.5

3300

207

4700

286

12.5

19.5

6800

404

19.5

39.5

10000

584

39.5

22000

1250

79.5

79.5

33000

1853

814.5

47000

2607

814.5

1. Specified by design. Not tested in production.

2. BOOSTEN and ANASWVDD configured properly according to V

DD

 and V

DDA

 values. 

3. Values without external capacitor.

4. The tolerance is 1 LSB.

5. The maximum value of R

AIN

 is obtained in a worst-case scenario: channel conversion in scan mode with channel i 

connected to V

REF+

 and channel i + 1 connected to V

REF-

.

Table 107. Maximum R

AIN

 for 12-bit ADC4

(1)(2)(3)

 (continued)

Resolution

(4)

R

AIN

 max (

)

(5)

Sampling time [ns] Sampling cycle at 35 MHz Sampling cycle at 55 MHz

Table 108. 12-bit ADC4 accuracy

(1)(2)

 

(3)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ET

Total unadjusted error

-

-

±3

±7.5

LSB

EO

Offset error

-

-

±2

±5.5

EG

Gain error

-

-

±2

±6.5

ED

Differential linearity error

-

-

-0.9/+1

-0.9/+1.5

EL

Integral linearity error

-

-

±2

±3.5

ENOB

Effective number of bits

-

9.9

10.9

-

bits

SINAD

Signal-to-noise and distortion ratio

-

61.4

67.4

-

dB

SNR

Signal-to-noise ratio

-

61.6

67.5

-

THD

Total harmonic distortion

-

-

-74

-70

1. Evaluated by characterization for BGA packages. Not tested in production. The values for LQFP packages may differ.

2. ADC DC accuracy values are measured after the internal calibration.

3. The I/O analog switch voltage booster is enabled when V

DDA

 < 2.4 V (BOOSTEN = 1 in SYSCFG_CFGR1 when 

V

DDA

 < 2.4 V). This switch is disabled when V

DDA

 

 2.4 V. Resolution = 12 bits, no oversampling.

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305

5.3.21 

Temperature sensor characteristics

          

5.3.22 V

CORE 

monitoring characteristics

          

5.3.23 V

BAT 

monitoring characteristics

          

Table 109. Temperature sensor characteristics 

Symbol

Parameter

Min

Typ

Max

Unit

T

L

(1)

V

SENSE

 linearity with temperature

-

-

1.3

°C

Avg_Slope

(1)

Average slope

2

2.5

3.0

mV/°C

V

30

(2)

Voltage at 30°C (±1 °C)

700

752

800

mV

(V

continuous

 - 

V

sampling

)

(3)

Difference of voltage between continuous and 
sampling modes

(4)

-

-

–10/+4

t

START

(TS_BUF)

(3)

Sensor buffer startup time

-

1

10

µs

t

S_temp

(3)

ADC sampling time when reading the temperature

13

-

-

I

DD(TS)

(3)

Temperature sensor consumption from V

DD

, when 

selected by ADC

-

14

20

µA

1. Evaluated by characterization. Not tested in production.

2. Measured at V

REF+

 = V

DDA

 = 3.0 V ±10 mV. The V

30

 A/D conversion result is stored in the TS_CAL1 byte. Refer to 

Table 16: Temperature sensor calibration values

.

3. Specified by design. Not tested in production.

4. The temperature sensor is in continuous mode when the regulator is in range 1, 2 or 3. The temperature sensor is in 

sampling mode when the regulator is in range 4, or when the device is in Stop 1 or Stop 2 mode.

Table 110. V

CORE

 monitoring characteristics

(1)

 

Symbol

Parameter

Min

Typ

Max

Unit

t

S_VCORE

ADC sampling time when reading the V

CORE

 

voltage

1

-

-

µs

1. Specified by design. Not tested in production.

Table 111. V

BAT

 monitoring characteristics

(1)

 

Symbol

Parameter

Min

Typ

Max

Unit

R

Resistor bridge for V

BAT

-

4 × 25.6

-

k

Q

Ratio on V

BAT

 measurement

-

4

-

-

Er

(2)

Error on Q

-5

-

5

%

t

S_VBAT

(2)

ADC sampling time when reading the VBAT

5

-

-

µs

1. 1.58 V 

 V

BAT

 

 3.6 V

2. Specified by design. Not tested in production.

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DS13737 Rev 10

          

5.3.24 Digital-to-analog 

converter characteristics

          

Table 112. V

BAT

 charging characteristics 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

R

BC

Battery charging resistor 

VBRS = 0

-

5

-

k

VBRS = 1

-

1.5

-

Table 113. DAC characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

DDA

Analog supply voltage for 
DAC ON

-

1.6

-

3.6 

V

V

REF+

Positive reference voltage

-

1.6

-

V

DDA

V

REF-

Negative reference voltage

-

-

V

SSA

-

R

L

Resistive load

DAC output 
buffer ON

connected to V

SSA

5

-

-

k

connected to 
V

DDA

25

-

-

R

O

Output impedance

DAC output buffer OFF

10

13

16

R

BON

Output impedance sample 
and hold mode, output 
buffer ON

V

DDA

 = 2.7 V

-

-

1.5

V

DDA 

= 2.0 V

-

-

2.5

R

BOFF

Output impedance sample 
and hold mode, output 
buffer OFF

V

DDA 

= 2.7 V

-

-

16.5

V

DDA 

= 2.0 V

-

-

17.5

C

L

Capacitive load

DAC output buffer OFF

-

-

50

pF

C

SH

Sample and hold mode

-

0.1

1

µF

V

DAC_OUT

Voltage on DAC_OUT 
output

DAC output buffer ON

0.2

-

V

DDA

 - 0.2 

V

DAC output buffer OFF

0

-

V

REF+

t

SETTLING

Settling time (full scale: for 
a 12-bit code transition 
between the lowest and the 
highest input codes when 
DAC_OUT reaches the 
final value of ±0.5 LSB, 
±1 LSB, ±2 LSB, ±4 LSB, 
or ±8 LSB)

Normal mode

 

DAC output 
buffer ON

 

C

L

 

 50 pF,

 

R

L

 

 5 k

±0.5 LSB

-

2.05

3.05

µs

±1 LSB

-

1.90

3

±2 LSB

-

1.85

2.85

±4 LSB

-

1.80

2.8

±8 LSB

-

1.75

2.65

Normal mode DAC output 
buffer OFF, ±1 LSB, C

L

 = 10 pF

-

1.7

3

t

WAKEUP

(2)

Wake-up time from off state 
(setting the ENx bit in the 
DAC control register) until 
the final value ±1 LSB

Normal mode DAC output buffer 
ON

 

C

L

 

 50 pF, R

L

 = 5 k

-

4.2

7.5

µs

Normal mode DAC output 
buffer OFF, C

L

 

 10 pF

-

2

5

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Electrical characteristics

305

PSRR

DC V

DDA

 supply rejection 

ratio

Normal mode DAC output buffer 
ON

 

C

L

 

 50 pF, R

L

 = 5 k

-

-80

-28

dB

t

SAMP

Sampling time in sample 
and hold mode, 
C

SH

 = 100 nF

 

(code transition between 
the lowest input code and 
the highest input code 
when DACOUT reaches 
the final value ±1 LSB)

DAC_OUT 
pin 
connected

DAC output buffer 
ON, C

SH 

= 100 nF

-

0.7

1.9

ms

DAC output buffer 
OFF, C

SH

 = 

100 nF

-

10.5

15

DAC_OUT 
pin not 
connected 
(internal 
connection 
only)

DAC output buffer 
OFF

-

2

8

µs

 I

leak

Output leakage current

-

-

-

(3)

nA

CI

int

Internal sample and hold 
capacitor

-

7

9.2

11

pF

t

TRIM

Middle code offset trim time DAC output buffer ON

50

-

-

µs

V

offset

Middle code offset for 
1 trim code step

V

REF+

 = 3.6 V

-

1520

-

µV

V

REF+

 = 1.6 V

-

680

-

I

DDA(DAC)

DAC consumption 
from V

DDA

DAC output 
buffer ON

No load, middle 
code (0x800)

-

330

510

µA

No load, worst 
code (0xF1C)

-

470

680

DAC output 
buffer OFF

No load, 
middle/worst code 
(0x800)

-

-

0.3

Sample and hold mode, 
C

SH

 = 100 nF

-

330 × T

ON

/(T

ON

 +

T

OFF

)

(4)

680 × T

ON

/(T

ON

 +

T

OFF

)

(4)

Table 113. DAC characteristics

(1)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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DS13737 Rev 10

Figure 41. 12-bit buffered/non-buffered DAC

          

I

DDV(DAC)

DAC consumption 
from V

REF+

DAC output 
buffer ON

No load, middle 
code (0x800)

-

170

240

µA

No load, worst 
code (0x0E4)

-

300

400

DAC output 
buffer OFF

No load, 
middle/worst code 
(0x800)

-

145

180

Sample and hold mode, buffer 
ON, C

SH

 = 100 nF (worst code)

-

170 × T

ON

/(T

ON

 +

T

OFF

)

(4)

400 × T

ON

/(T

ON

 +

T

OFF

)

(4)

Sample and hold mode, buffer 
OFF, C

SH

 = 100 nF (worst code)

-

145 × T

ON

/(T

ON

 +

T

OFF

)

(4)

180 × T

ON

/(T

ON

 +

T

OFF

)

(4)

1. Specified by design. Not tested in production.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).

3. Refer to 

Table 93: I/O static characteristics

.

4. T

ON

 is the refresh phase duration. T

OFF

 is the hold phase duration (see the product reference manual for more details).

Table 113. DAC characteristics

(1)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MSv47959V2

12-bit 

digital-to-analog 

converter

Buffered/non-buffered DAC

DAC_OUTx

R

LOAD

C

LOAD

Buffer

(1)

(1) The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads 
directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in 
the DAC_CR register.  

Table 114. DAC accuracy

(1)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

DNL

Differential 
non-linearity

(2)

DAC output buffer ON

-

-

±2

LSB

DAC output buffer OFF

-

-

±2

-

Monotonicity

10 bits

guaranteed

-

INL

Integral 
non-linearity

(3)

DAC output buffer ON, C

L

 

 50 pF, R

L

 

 5 k

-

-

±4

LSB

DAC output buffer OFF, C

L

 

 50 pF, no R

L

-

-

±4

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305

Offset

Offset error at code 
0x800

(3)

DAC output buffer OFF, C

L

 

 50 pF, no R

L

-

-

±8

LSB

Offset1

Offset error at code 
0x001

(4)

DAC output buffer OFF, C

L

 

 50 pF, no R

L

-

-

±5

OffsetCal

Offset error at code 
0x800

(3)

 

after calibration

DAC output buffer ON, 
C

L

 

 50 pF, R

L

 

 5 k

V

REF+

 = 3.6 V

-

-

±5

V

REF+

 = 1.6 V

-

-

±5

Gain

Gain error

(5)

DAC output buffer ON, C

L

 

 50 pF, R

L

 

 5 k

-

-

±0.5

%

DAC output buffer OFF, C

L

 

 50 pF, no R

L

-

-

±0.5

TUE

Total unadjusted error

DAC output buffer OFF, C

L

 

 50 pF, no R

L

-

-

±10

LSB

DAC output buffer ON, C

L

 

 50 pF, R

L

 

 5 k

,

 

after calibration

-

-

±14

SNR

Signal-to-noise 
ratio

(6)

DAC output buffer ON, C

L

 

 50 pF, R

L

 

 5 k

1 kHz, BW = 500 kHz

-

70.6

-

dB

DAC output buffer OFF, C

L

 

 50 pF, no R

L

, 1 kHz, 

BW = 500 kHz

-

72

-

THD

Total harmonic 
distortion

(6)

DAC output buffer ON, C

L

 

 50 pF, R

L

 

 5 k

, 1 kHz

-

-79

-

DAC output buffer OFF, C

L

 

 50 pF, no R

L

, 1 kHz

-

-81

-

SINAD

Signal-to-noise and 
distortion ratio

(6)

DAC output buffer ON, C

L

 

 50 pF, R

L

 

 5 k

, 1 kHz

-

70.1

-

DAC output buffer OFF, C

L

 

 50 pF, no R

L

, 1 kHz

-

71.5

-

ENOB

Effective number 
of bits

DAC output buffer ON, C

L

 

 50 pF, R

L

 

 5 k

, 1 kHz

-

11.3

-

bits

DAC output buffer OFF, C

L

 

 50 pF, no R

L

, 1 kHz

-

11.6

-

1. Specified by design. Not tested in production.

2. Difference between two consecutive codes minus 1 LSB.

3. Difference between the value measured at code i and the value measured at code i on a line drawn between code 0 and 

last code 4095.

4. Difference between the value measured at code (0x001) and the ideal value.

5. Difference between the ideal transfer-function slope and the measured slope computed from code 0x000 and 0xFFF when 

the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.

6. Signal is -0.5 dBFS with Fsampling = 1 MHz.

Table 114. DAC accuracy

(1)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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DS13737 Rev 10

5.3.25 Voltage 

reference buffer characteristics

          

Table 115. VREFBUF characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

DDA

Analog supply 
voltage 

Normal mode

VRS = 000

1.8

-

3.6

V

VRS = 001

2.1

-

VRS = 010

2.4

-

VRS = 011

2.8

-

Degraded 
mode

(2)

VRS = 000

1.62

-

1.8

VRS = 001

-

2.1

VRS = 010

-

2.4

VRS = 011

-

2.8

V

REFBUF

_OUT

(3)

Voltage reference 
buffer output 

Normal mode at 
V

DDA

 = 3 V, 

T

J

 = 30 °C, 

I

load

 = 10 µA

VRS = 000

1.496

1.5

1.504

VRS = 001

1.795

1.8

1.805

VRS = 010

2.042

2.048

2.054

VRS = 011

2.493

2.5

2.507

Degraded 
mode

(2)

VRS = 000

Min (V

DDA

 - 0.15

;1.496)

-

1.504

VRS = 001

Min (V

DDA

 - 0.15

;1.795)

-

1.805

VRS = 010

Min (V

DDA

 - 0.15

;2.042)

-

2.054

VRS = 011

Min (V

DDA

 - 0.15

;2.493)

-

2.507

TRIM

Trim step

-

0.1

0.175

0.25

%

C

L

Load capacitor

(4)

-

0.5

1.10

1.50

µF

esr

C

equivalent serial 

resistor

-

-

-

2

I

load

Static load current

-

-

-

4

mA

R

PD

Pull-down resistance

-

-

-

400

I

line_reg 

Line regulation

V

DDAmin

 

 V

DDA 

 3.6 V,

 

Normal mode,

 

500 µA 

 I

load

 

 4 mA

±0.016

±0.033

±0.053

%

I

load_reg

Load regulation

(5)

Normal mode,

 

500 

μ

 I

load

 

 4 mA

-

50

400

ppm/

mA

T

Coeff

Temperature 
coefficient

–40 °C < T

J

 < +130 °C

-

-

T

coeff_vrefint

 

+ 50

ppm/

°C

PSRR

Power supply 
rejection

DC

-

65

-

dB

100 kHz

-

30

-

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Figure 42. V

REFBUF_OUT

 versus temperature (VRS = 000)

t

START

Startup time

C

L

 = 0.5 µF

-

110

200

µs

C

L

 = 1.1 µF

-

240

350

C

L

 = 1.5 µF

-

320

500

I

INRUSH

Control of DC 
current drive on 
V

REFBUF_

 

OUT

 during startup 

phase 

(6)

-

-

8

11

mA

I

DDA

(VREFBUF

)

VREFBUF 
consumption from 
V

DDA

I

load

 = 0 µA

-

14

18

µA

I

load

 = 500 µA

-

16

20

I

load 

= 4 mA

-

42

50

1. Specified by design and not tested in production, unless otherwise specified.

2. In degraded mode, the voltage reference buffer can not accurately maintain the output voltage (V

DDA

 - drop voltage).

3. Evaluated by characterization. Not tested in production.

4. The capacitive load must include a 100 nF capacitor in order to cut off the high-frequency noise.

5. The load regulation value only takes into account the die and package resistance. The parasitic resistance on PCB 

degrades this value.

6. To correctly control the VREFBUF inrush current during startup phase and scaling change, the V

DDA

 voltage must be in the 

range of [1.8 V-3.6 V], [2.1 V-3.6 V], [2.4 V-3.6 V] and [2.8 V-3.6 V] for VRS = 000, 001, 010 and 011 respectively.

Table 115. VREFBUF characteristics

(1)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MSv69705V1

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DS13737 Rev 10

Figure 43. V

REFBUF_OUT

 versus temperature (VRS = 001)

Figure 44. V

REFBUF_OUT

 versus temperature (VRS = 010)

Figure 45. V

REFBUF_OUT

 versus temperature (VRS = 011)

MSv69706V1

MSv69707V1

MSv69708V1

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305

5.3.26 Comparator 

characteristics

          

Table 116. COMP characteristics

(1)(2)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

DDA

Analog supply voltage for 
COMP ON

-

1.58

-

3.6

V

V

IN

Comparator input voltage 
range

-

0

-

V

DDA

V

REFINT

(3)

Scaler input voltage

-

(3)

V

SC

Scaler offset voltage

-

-

±5

±10

mV

I

DDA(SCALER)

Scaler static consumption 
from V

DDA

Scaler bridge disabled

(4)

-

0.20

0.25

µA

Scaler bridge enabled

(5)

-

0.7

1

t

START_SCALER

Scaler startup time

-

-

130

220

µs

t

START

Comparator startup time to 
reach propagation delay 
specification

High-speed mode

-

-

5

Medium mode

-

-

25

Ultra-low-power mode

-

-

80

t

D

(6)

Propagation delay for 
200 mV step with 100 mV 
overdrive

High-speed mode

-

40

100

ns

Medium mode

-

0.5

1

µs

Ultra-low-power mode

-

2

7

V

offset

Comparator offset error

Full common mode range

-

±5

±20

mV

V

hys

Comparator hysteresis

No hysteresis

-

0

-

Low hysteresis

-

15

-

Medium hysteresis

-

30

-

High hysteresis

-

45

-

I

bias

Comparator input bias 
current

-

(7)

nA

I

DDA(COMP)

Comparator consumption 
from V

DDA

 

High-speed mode, static

-

48

90

µA

High-speed mode, with 50 kHz, 
±100 mV overdrive square signal

-

50

-

Medium mode, static

-

3

6

Medium mode, with 50 kHz, ±100 mV 
overdrive square signal

-

3.75

-

Ultra-low-power mode, static

-

0.3

1

Ultra-low-power mode, with 50 kHz, 
±100 mV overdrive square signal

-

0.65

1. Specified by design and not tested in production, unless otherwise specified.

2. The input capacitance is negligible compared to the I/O capacitance.

3. Refer to 

Table 36: Embedded internal voltage reference

.

4. No V

REFINT

 division, includes only buffer consumption.

5. V

REFINT

 division, includes resistor bridge and buffer consumption.

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DS13737 Rev 10

5.3.27 Operational 

amplifiers characteristics

          

6. Evaluated by characterization. Not tested in production.

7. Mostly I/O leakage when used in analog mode. Refer to I

lkg

 parameter in 

Table 93: I/O static characteristics

.

Table 117. OPAMP characteristics

(1)(2)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

DDA

Analog supply voltage 
range for OPAMP ON

-

1.60

-

3.6

V

CMIR

Common mode input 
range

-

0

-

V

DDA

VI

OFFSET

Input offset voltage

T

J

 = 30 °C, no load on output,

 

Normal mode

-

-

±3

mV

T

J

= 30 °C, no load on output,

 

Low-power mode

-

-

±3

All voltages and temperature, 

 

Normal mode

-

-

±7

All voltages and temperature, 

 

Low-power mode

-

-

±11.5

VI

OFFSET

Input offset voltage drift 
over temperature

Normal mode

-

±7

-

μ

V/°C

Low-power mode

-

±15

-

TRIMOFFSETP 

TRIMLPOFFSETP

Offset trim step at low 
common input voltage 
(0.1 × V

DDA

)

-

-

1.05

1.25

mV

TRIMOFFSETN 

TRIMLPOFFSETN

Offset trim step at high 
common input voltage 
(0.9 × V

DDA

)

-

-

1.05

1.25

I

LOAD

Drive current

Normal mode

-

-

500

μ

A

Low-power mode

-

-

100

I

LOAD_PGA

Drive current in PGA mode

Normal mode

-

-

450

Low-power mode

-

-

50

R

LOAD

Resistive load (connected 
to VSSA or VDDA)

Normal mode

3.9

-

-

k

Low-power mode

20

-

-

C

LOAD

Capacitive load

-

-

-

50

pF

CMRR

Common mode rejection 
ratio

Normal mode

-

79

-

dB

Low-power mode

-

69

-

PSRR

Power supply rejection 
ratio

Normal 
mode

C

LOAD

 

 50 pF, 

 

R

LOAD

 

 3.9 k

(3)

DC

35

75

-

dB

Low-power 
mode

C

LOAD

 

 50 pF,

 

R

LOAD

 

 20 k

(3)

DC

32

69

-

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GBW

Gain bandwidth product

Normal mode

0.4

2

3.1

MHz

Low-power mode

0.23

0.5

0.76

SR

(3)

Slew rate (from 10% and 
90% of output voltage)

Normal 
mode

Standard speed 
mode 
(OPAHSM = 0) 

0.5

1

3.2

V/µs

Low-power 
mode

0.14

0.25

0.75

Normal 
mode

High speed mode 
(OPAHSM = 1) 

1.4

3.2

5.6

Low-power 
mode

0.38

0.82

1.5

AO

Open loop gain

Normal mode

72

105

-

dB

Low-power mode

77

106

-

φ

m

Phase margin

Normal mode

54

67

-

°

Low-power mode

54

65

-

GM

Gain margin

Normal mode

-

9

-

dB

Low-power mode

-

17

-

V

OHSAT

(3)

High saturation voltage

Normal 
mode

I

LOAD

 max or 

R

LOAD

 min,

 

Input at V

DDA

V

DDA

- 100

-

-

mV

Low-power 
mode

V

DDA

- 50

-

-

V

OLSAT

(3)

Low saturation voltage

Normal 
mode

I

LOAD

 max or 

R

LOAD

 min,

 

Input at 0 V

-

-

100

Low-power 
mode

-

-

50

t

WAKEUP

Wake-up time from 
OFF state

Normal 
mode

C

LOAD

 

 50 pF,

 

R

LOAD

 

 3.9 k

follower config.

-

4

10

µs

Low-power 
mode

C

LOAD

 

 50 pF, 

 

R

LOAD

 

 20k

follower config.

-

20

40

I

bias

OPAMP input bias current

General purpose input (all 
packages except UFBGA)

-

-

(4)

nA

Dedicated 
input 
(UFBGA 
only)

T

J

 

 75 °C

-

-

7

T

J

 

 85 °C

-

-

9

T

J

 

 105 °C

-

-

18

T

J

 

 125 °C

-

-

25

Table 117. OPAMP characteristics

(1)(2)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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DS13737 Rev 10

PGA gain

(3)

Non-inverting gain value

PGA_GAIN[1:0] = 00

-

2

-

-

PGA_GAIN[1:0] = 01

-

4

-

PGA_GAIN[1:0] = 10

-

8

-

PGA_GAIN[1:0] = 11

-

16

-

Rnetwork

R2/R1 internal resistance 
values in non-inverting 
PGA mode

(5)

PGA gain = 2

-

80/80

-

k

k

PGA gain = 4

-

120/40

-

PGA gain = 8

-

140/20

-

PGA gain = 16

-

150/10

-

Delta R

Resistance variation 
(R1 or R2)

-

-18

-

18

%

PGA gain error

PGA gain error

-

-1

-

1

PGA BW

PGA bandwidth for 
different non inverting gain

PGA gain = 2

-

GBW/2

-

MHz

PGA gain = 4

-

GBW/4

-

PGA gain = 8

-

GBW/8

-

PGA gain = 16

-

GBW/16

-

en

Voltage noise density

Normal 
mode

At 1 kHz, 

 

output loaded with 
3.9 k

-

220

-

nV

/

Hz

Low-power 
mode

At 1 kHz, 

 

output loaded with 
20 k

-

350

-

Normal 
mode

At 10 kHz, output 
loaded with 3.9 k

-

190

-

Low-power 
mode

at 10 kHz, output 
loaded with 20 k

-

210

-

I

DDA(OPAMP)

OPAMP consumption from 
V

DDA

Normal 
mode

no load, quiescent 
mode,

 

standard speed

-

130

190

µA

Low-power 
mode

-

40

58

Normal 
mode

no load, quiescent 
mode, 

 

high-speed mode

-

138

205

Low-power 
mode

-

42

60

1. Specified by design and not tested in production, unless otherwise specified.

2. OPA_RANGE must be set to 1 in OPAMP1_CSR.

3. Evaluated by characterization. Not tested in production.

4. Mostly I/O leakage when used in analog mode. Refer to I

lkg

 parameter in 

Table 93: I/O static characteristics

.

5. R2 is the internal resistance between the OPAMP output and the OPAMP inverting input. R1 is the internal resistance 

between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.

Table 117. OPAMP characteristics

(1)(2)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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Figure 46. OPAMP voltage noise density, normal mode, R

LOAD

 = 3.9 k

Figure 47. OPAMP voltage noise density, low-power mode, R

LOAD

 = 20 k

5.3.28 Temperature 

and backup domain supply thresholds monitoring

The temperature and backup domain supply monitoring characteristics are provided 
in the technical note STM32U54xxx/STM32U58xxx/STM32U5Axxx/STM32U5Gxxx MCUs 
for PCI products (TN1333) (NDA required).

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DS13737 Rev 10

5.3.29 ADF/MDF 

characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests 
performed under the ambient temperature, f

AHB

 frequency and V

DD

 supply voltage 

conditions summarized in 

Table 32

, with the following configuration:

Output speed set to OSPEEDRy[1:0] = 10

Capacitive load C

L

 = 30 pF

Measurement points done at 0.5

 × 

V

DD

 level

I/O compensation cell activated 

HSLV activated when V

DD

 

 2.7 V 

Voltage scaling range 1

Refer to 

Section 5.3.15: I/O port characteristics

 for more details on the input/output alternate 

function characteristics.

          

Table 118. ADF characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Typ Max Unit

f

CCKI

Input clock frequency via 
ADF_CCK[1:0] pin, in SLAVE 
SPI mode

1.71 

 V

DD

 

 3.6 V

-

-

25

MHz

f

CCKO

Output clock frequency in 
MASTER SPI mode

-

-

25

f

CCKOLF

Output clock frequency in 
LF_MASTER SPI mode

-

-

5

f

SYMB

Input symbol rate in 
Manchester mode

-

-

20

t

HCCKI

 

t

LCCKI

ADF_CCK[1:0] input clock 
high and low time 

In SLAVE SPI mode

2 ×

Tadf_proc_ck

(2)

-

-

ns

t

HCCKO

 

t

LCCKO

ADF_CCK[1:0] output clock 
high and low time 

In MASTER SPI mode

2 ×

Tadf_proc_ck

-

-

t

HCCKOLF

 

t

LCCKOLF

ADF_CCK[1:0] output clock 
high and low time 

In LF_MASTER SPI mode

 Tadf_proc_ck

-

-

t

SUCCKI

Data setup time with respect 
to ADF_CCK[1:0] input

In SLAVE SPI mode: 
ADF_CCK[1:0] configured in 
input, measured on rising and 
falling edge

4.5

-

-

t

HDCCKI

Data hold time with respect to 
ADF_CCK[1:0] input

1

-

-

t

SUCCKO

Data setup time with respect 
to ADF_CCK[1:0] output

In MASTER SPI mode: 
ADF_CCK[1:0] configured in 
output, measured on rising and 
falling edge

5.5

-

-

t

HDCCKO

Data hold time with respect to 
ADF_CCK[1:0] output

0

-

-

t

SUCCKOLF

Data setup time with respect 
to ADF_CCK[1:0] output

In LF_MASTER SPI mode: 
ADF_CCK[1:0] configured in 
output, measured on rising and 
falling edge

19.5

-

-

ns

t

HDCCKOLF

Data hold time with respect to 
ADF_CCK[1:0] output

0

-

-

1. Evaluated by characterization. Not tested in production.

2. Tadf_proc_ck is the period of the ADF processing clock.

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Figure 48. ADF timing diagram

          

MSv69124V1

ADF_SDIx (I)

ADF_CCK (I/O)

t

SUCCKI

t

SUCCKO

t

SUCCKOLF

f

CCKI

, f

CCKO

, f

CCKOLF

t

LCCKI

, t

LCCKO

t

LCCKOLF

t

HDCCKI

t

HDCCKO

t

HDCCKOLF

t

HCCKI

, t

HCCKO

t

HCCKOLF

t

SUCCKI

t

SUCCKO

t

SUCCKOLF

t

HDCCKI

t

HDCCKO

t

HDCCKOLF

Table 119. MDF characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Typ

Max Unit

f

CKI

Input clock frequency via 
MDF_CKIx pin, in 
SLAVE SPI mode

1.71 

 V

DD

 

 3.6 V

-

-

25

MHz

f

CCKI

Input clock frequency via 
MDF_CCK[1:0] pin, in 
SLAVE SPI mode

-

-

25

f

CCKO

Output clock frequency in 
MASTER SPI mode

-

-

25

f

CCKOLF

Output clock frequency in 
LF_MASTER SPI mode

-

-

5

f

SYMB

Input symbol rate in 
Manchester mode

-

-

20

t

HCKI 

t

LCKI

MDF_CKIx input clock high 
and low time 

In SLAVE SPI mode

2 ×

Tmdf_proc_ck

(2)

-

-

ns

t

HCCKI 

t

LCCKI

MDF_CCK[1:0] input clock 
high and low time 

In SLAVE SPI mode

2 ×

Tmdf_proc_ck

-

-

t

HCCKO 

t

LCCKO

MDF_CCK[1:0] output clock 
high and low time 

In MASTER SPI mode

2 ×

Tmdf_proc_ck

-

-

t

HCCKOLF 

t

LCCKOLF

MDF_CCK[1:0] output clock 
high and low time 

In LF_MASTER SPI mode

Tmdf_proc_ck

-

-

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DS13737 Rev 10

Figure 49. MDF timing diagram

t

SUCKI

Data setup time with respect 
to MDF_CKIx input

In SLAVE SPI mode, measured 
on rising and falling edge

1.5

-

-

ns

t

HDCKI

Data hold time with respect 
to MDF_CKIx input

0

-

-

t

SUCCKI

Data setup time with respect 
to MDF_CCK[1:0] input

In SLAVE SPI mode: 
MDF_CCK[1:0] configured in 
input, measured on rising and 
falling edge

1.5

-

-

t

HDCCKI

Data hold time with respect 
to MDF_CCK[1:0] input

0.5

-

-

t

SUCCKO

Data setup time with respect 
to MDF_CCK[1:0] output

In MASTER SPI mode: 
MDF_CCK[1:0] configured in 
output, measured on rising and 
falling edge

3.5

-

-

t

HDCCKO

Data hold time with respect 
to MDF_CCK[1:0] output

1.5

-

-

t

SUCCKOLF

Data setup time with respect 
to MDF_CCK[1:0] output

In LF_MASTER SPI mode, 
MDF_CCK[1:0] configured in 
output, measured on rising and 
falling edge

19.5

-

-

t

HDCCKOLF

Data hold time with respect 
to MDF_CCK[1:0] output

0

-

-

1. Evaluated by characterization. Not tested in production.

2. Tmdf_proc_ck is the period of the MDF processing clock.

Table 119. MDF characteristics

(1)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

MSv69125V1

MDF_SDIx (I)

MDF_CKIx (I)
MDF_CCK (I/O)

t

SUCKI

t

SUCCKI

t

SUCCKO

t

SUCCKOLF

f

CKI

, f

CCKI, 

F

CCKO

, f

CCKOLF

t

LCKI, 

t

LCCKI

t

LCCKO

t

HDCKI

t

HDCCKI

t

HDCCKO

t

HDCCKOLF

t

HCKI, 

t

HCCKI

t

HCCKO

t

SUCKI

t

SUCCKI

t

SUCCKO

t

SUCCKOLF

t

HDCKI

t

HDCCKI

t

HDCCKO

t

HDCCKOLF

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5.3.30 DCMI 

characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests 
performed under the ambient temperature, f

HCLK

 frequency and V

DD

 supply voltage 

summarized in 

Table 32

, with the following configuration:

Output speed set to OSPEEDRy[1:0] = 10

DCMI_PIXCLK polarity: falling

DCMI_VSYNC and DCMI_HSYNC polarity: high

Data formats: 14 bits

Capacitive load C

L

 = 30 pF

Measurement points done at 0.5

 × 

V

DD

 level

I/O compensation cell activated 

HSLV activated when V

DD

 

 2.7 V 

Voltage scaling range 1

          

Figure 50. DCMI timing diagram

Table 120. DCMI characteristics

(1)

 

Symbol

Parameter

Min

Max

Unit

-

Frequency ratio DCMI_PIXCLK/f

HCLK

-

0.4

-

DCMI_PIXCLK

Pixel clock input

-

64

MHz

D

PIXEL

Pixel clock input duty cycle

30

70

%

t

su(DATA)

Data input setup time

2

-

ns

t

h(DATA)

Data hold time

1

-

t

su(HSYNC)

t

su(VSYNC)

DCMI_HSYNC and DCMI_VSYNC input setup times

2

-

t

h(HSYNC)

t

h(VSYNC)

DCMI_HSYNC and DCMI_VSYNC input hold times

1

-

1. Evaluated by characterization. Not tested in production.

MS32414V2

DCMI_PIXCLK

t

su(VSYNC)

t

su(HSYNC)

DCMI_HSYNC

DCMI_VSYNC

DATA[0:13]

1/DCMI_PIXCLK

t

h(HSYNC)

t

h(HSYNC)

t

su(DATA)

t

h(DATA)

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DS13737 Rev 10

5.3.31 PSSI 

characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests 
performed under the ambient temperature, f

HCLK

 frequency and V

DD

 supply voltage 

summarized in 

Table 32

, with the following configuration:

Output speed set to OSPEEDRy[1:0] = 10

PSSI_PDCK polarity: falling

PSSI_RDY and PSSI_DE polarity: low

Bus width: 16 lines

Data width: 32 bits 

Capacitive load C

L

 = 30 pF

Measurement points done at 0.5

 × 

V

DD

 level

I/O compensation cell activated 

HSLV activated when V

DD

 

 2.7 V 

Voltage scaling range 1

          

Table 121. PSSI transmit characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Max

Unit

-

Frequency ratio DCMI_PDCK/f

HCLK

-

-

0.4

-

PSSI_PDCK PSSI clock input

2.7 V 

 V

DD

 

 3.6 V

-

64

(2)

MHz

1.71 V 

 V

DD

 

 3.6 V

-

47

(2)

D

PIXEL

PSSI clock input duty cycle

-

30

70

%

t

OV(DATA)

Data output valid time

2.7 V 

 V

DD

 

 3.6 V

-

14

ns

1.71 V 

 V

DD

 

 3.6 V

-

21

t

OH(DATA)

Data output hold time

1.71 V 

 V

DD

 

 3.6 V

7

-

t

OV(DE)

DE output valid time

-

12.5

t

OH(DE)

DE output hold time

6

-

t

SU(RDY)

RDY input setup time

1.71 V 

 V

DD

 

 3.6 V

0

-

t

H(RDY)

RDY input hold time

0

-

1. Evaluated by characterization. Not tested in production.

2. This maximal frequency does not consider receiver setup and hold timings.

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Figure 51. PSSI transmit timing diagram

          

MSv63437V1

t

s(RDY)

t

ho(DATA)

t

v(DATA)

CKPOL=0

PSSI_PDCK 

(input)

CKPOL=1

PSSI D[15:0]

(output)

t

h(RDY)

t

w(PDCKL)

t

w(PDCKH)

t

c(PDCK)

t

f(PDCK)

Invalid data OUT

Valid data OUT

DEPOL=0

PSSI_DE

(output)

DEPOL=1

RDYPOL=0

PSSI_RDY

(input)

RDYPOL=1

Invalid data OUT

t

r(PDCK)

t

v(DE)

t

ho(DE)

Table 122. PSSI receive characteristics

(1)

 

Symbol

Parameter

Conditions

Min

Max

Unit

-

Frequency ratio DCMI_PDCK/f

HCLK

-

-

0.4

-

PSSI_PDCK PSSI clock input

1.71 V 

 V

DD

 

 3.6 V

-

64

MHz

D

PIXEL

PSSI clock input duty cycle

-

30

70

%

t

SU(DATA)

Data input setup time

1.71 V 

 V

DD

 

 3.6 V

2

-

ns

t

H(DATA)

Data input hold time

1.5

-

t

SU(DE)

DE input setup time

0.5

-

t

H(DE)

DE input hold time

2

-

t

OV(RDY)

RDY output valid time

-

12

t

OH(RDY)

RDY output hold time

6

-

1. Evaluated by characterization. Not tested in production.

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Figure 52. PSSI receive timing diagram

5.3.32 Timer 

characteristics

The parameters given in the following tables are specified by design, not tested in 
production.

Refer to 

Section 5.3.15: I/O port characteristics

 for details on the input/output alternate 

function characteristics (output compare, input capture, external clock, PWM output).

          

MSv63436V1

t

s(DATA)

CKPOL=0

PSSI_PDCK

(input) 

CKPOL=1

PSSI D[15:0]

(input)

t

h(DATA)

t

w(PDCKL)

t

w(PDCKH)

t

c(PDCK)

t

f(PDCK)

Invalid data IN

Valid data IN

DEPOL=0

PSSI_DE

(input)

DEPOL=1

RDYPOL=0

PSSI_RDY

(output)

RDYPOL=1

Invalid data IN

t

r(PDCK)

t

s(DE)

t

h(DE)

t

v(RDY)

t

ho(RDY)

Table 123. TIMx

(1)

 characteristics 

Symbol

Parameter

Conditions

Min

Max

Unit

t

res(TIM)

Timer resolution time

-

1

-

t

TIMxCLK

f

TIMxCLK

 = 160 MHz

6.25

-

ns

f

EXT

Timer external clock frequency on 
CH1 to CH4

-

0

f

TIMxCLK

/2

MHz

f

TIMxCLK

 = 160 MHz

0

80

Res

TIM

Timer resolution

TIMx (except TIM2/3/4/5)

-

16

bit

TIM2/3/4/5

-

32

t

COUNTER

16-bit counter clock period

-

1

65536

t

TIMxCLK

f

TIMxCLK

 = 160 MHz

0.007

409.6

µs

t

MAX_COUNT

Maximum possible count with 
32-bit counter

-

-

65536 × 65536 t

TIMxCLK

f

TIMxCLK

 = 160 MHz

-

26.843

s

1. TIMx

is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.

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5.3.33 FSMC 

characteristics

Unless otherwise specified, the parameters given in the tables below are derived from tests 
performed under the ambient temperature, f

HCLK

 frequency and V

DD

 supply voltage 

conditions summarized in 

Table 32

, with the following configuration:

Output speed set to OSPEEDRy[1:0] = 10

Capacitive load C

L

 = 30 pF, unless otherwise specified

Measurement points done at 0.5

 × 

V

DD

 level

I/O compensation cell activated

HSLV activated when V

DD

 

 2.7 V 

Voltage scaling range 1

Refer to 

Section 5.3.15: I/O port characteristics

 for more details on the input/output 

characteristics.

Table 124. IWDG min/max timeout period at 32 kHz (LSI)

(1)

 

Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000

Max timeout RL[11:0] = 0xFFF

Unit

/4

0

0.125

512

ms

/8

1

0.250

1024

/16

2

0.500

2048

/32

3

1.0

4096

/64

4

2.0

8192

/128

5

4.0

16384

/256

6 or 7

8.0

32768

1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock, so that there is always a full 

RC period of uncertainty.

Table 125. WWDG min/max timeout value at 160 MHz (PCLK) 

Prescaler

WDGTB

Min timeout value

Max timeout value

Unit

1

0

0.025

1.638

ms

2

1

0.051

3.276

4

2

0.102

6.553

8

3

0.204

13.107

16

4

0.409

26.214

32

5

0.819

52.428

46

6

1.177

75.366

128

7

3.276

209.715

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Asynchronous waveforms and timings

Figure 53

 to 

Figure 56

 represent asynchronous waveforms and 

Table 126

 to 

Table 133

 

provide the corresponding timings. The results shown in these tables are obtained with the 
following FMC configuration:

AddressSetupTime (ADDSET) = 0x1

AddressHoldTime (ADDHLD) = 0x1

ByteLaneSetup (NBLSET) = 0x1

DataSetupTime (DATAST) = 0x1 (except for asynchronous NWAIT mode, 
DataSetupTime = 0x5)

DataHoldTime (DATAHLD) = 0x1 (0x0 for write operation)

BusTurnAroundDuration = 0x0

Capacitive load C

L

 = 30 pF

In all timing tables, the T

HCLK

 is the HCLK clock period.

Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

Data

FMC_NE

FMC_NBL[1:0]

FMC_D[15:0]

t

v(BL_NE)

t

h(Data_NE)

FMC_NOE

Address

FMC_A[25:0]

t

v(A_NE)

FMC_NWE

t

su(Data_NE)

t

w(NE)

MS32753V1

w(NOE)

t

t

v(NOE_NE)

t

h(NE_NOE)

t

h(Data_NOE)

t

h(A_NOE)

t

h(BL_NOE)

t

su(Data_NOE)

FMC_NADV

(1)

t

v(NADV_NE)

t

w(NADV)

FMC_NWAIT

tsu(NWAIT_NE)

th(NE_NWAIT)

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Table 126. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

(1)

 

Symbol

Parameter

Min

Max

Unit

t

w(NE)

FMC_NE low time

3 × t

HCLK

 - 1

3 × t

HCLK

 + 1

ns

t

v(NOE_NE)

FMC_NEx low to FMC_NOE low

0

5

t

w(NOE)

FMC_NOE low time

2 × t

HCLK

 - 1

2 × t

HCLK

 + 1

t

h(NE_NOE)

FMC_NOE high to FMC_NE high hold time

T

HCLK

-

t

v(A_NE)

FMC_NEx low to FMC_A valid

-

1.5

t

h(A_NOE)

Address hold time after FMC_NOE high

2 × t

HCLK

 - 1

-

t

su(Data_NE)

Data to FMC_NEx high setup time

t

HCLK

 + 15

-

t

su(Data_NOE)

Data to FMC_NOEx high setup time

15

-

t

h(Data_NOE)

Data hold time after FMC_NOE high

0

-

t

h(Data_NE)

Data hold time after FMC_NEx high

0

-

t

v(NADV_NE)

FMC_NEx low to FMC_NADV low

-

1.5

t

w(NADV)

FMC_NADV low time

-

T

HCLK

 + 1

1. Evaluated by characterization. Not tested in production.

Table 127. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings

(1)

 

Symbol

Parameter

Min

Max

Unit

t

w(NE)

FMC_NE low time

8 × t

HCLK

 - 1

8 × t

HCLK

 + 1

ns

t

w(NOE)

FMC_NWE low time

7 × t

HCLK

 - 1

7 × t

HCLK

 + 1

t

w(NWAIT)

FMC_NWAIT

(2)

 low time

t

HCLK

 -

t

su(NWAIT_NE)

FMC_NWAIT valid before FMC_NEx high

5 × t

HCLK

 + 9.5

-

t

h(NE_NWAIT)

FMC_NEx hold time after FMC_NWAIT invalid

4 × t

HCLK

 + 10

-

1. Evaluated by characterization. Not tested in production.

2. NWAIT pulse is equal to one HCLK cycle.

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Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

          

NBL

Data

FMC_NEx

FMC_NBL[1:0]

FMC_D[15:0]

tv(BL_NE)

th(Data_NWE)

FMC_NOE

Address

FMC_A[25:0]

tv(A_NE)

tw(NWE)

FMC_NWE

tv(NWE_NE)

t h(NE_NWE)

th(A_NWE)

th(BL_NWE)

tv(Data_NE)

tw(NE)

MS32754V1

FMC_NADV (1)

t v(NADV_NE)

tw(NADV)

FMC_NWAIT

tsu(NWAIT_NE)

th(NE_NWAIT)

Table 128. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

(1)

 

Symbol

Parameter

Min

Max

Unit

t

w(NE)

FMC_NE low time

3 × t

HCLK

 - 1

3 × t

HCLK

 + 1

ns

t

v(NWE_NE)

FMC_NEx low to FMC_NWE low

t

HCLK

 - 1

t

HCLK

 + 1

t

w(NWE)

FMC_NWE low time

t

HCLK

 - 0.5

t

HCLK

 + 0.5

t

h(NE_NWE)

FMC_NWE high to FMC_NE high hold time

t

HCLK

 -

t

v(A_NE)

FMC_NEx low to FMC_A valid

 -

1

t

h(A_NWE)

Address hold time after FMC_NWE high

t

HCLK

 - 0.5

 -

t

v(BL_NE)

FMC_NEx low to FMC_BL valid 

 -

0.5

t

h(BL_NWE)

FMC_BL hold time after FMC_NWE high

t

HCLK

 - 0.5

 -

t

v(Data_NE)

FMC_NEx low to Data valid

 -

t

HCLK

 + 2

t

h(Data_NWE)

Data hold time after FMC_NWE high

t

HCLK

 -

t

v(NADV_NE)

FMC_NEx low to FMC_NADV low

 -

2

t

w(NADV)

FMC_NADV low time

 -

t

HCLK

 + 1

1. Evaluated by characterization. Not tested in production.

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Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms

Table 129. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings

(1)

 

Symbol

Parameter

Min

Max

Unit

t

w(NE)

FMC_NE low time

8 × t

HCLK

 - 1

8 × t

HCLK

 + 1

ns

t

w(NWE)

FMC_NWE low time

6 × t

HCLK

 - 1

6 × t

HCLK

 + 1

t

su(NWAIT_NE)

FMC_NWAIT

(2)

 valid before FMC_NEx high

5 × t

HCLK

 + 13

-

t

h(NE_NWAIT)

FMC_NEx hold time after FMC_NWAIT invalid

4 × t

HCLK

 + 12

-

1. Evaluated by characterization. Not tested in production.

2. NWAIT pulse is equal to one HCLK cycle.

NBL

Data

FMC_ NBL[1:0]

FMC_ AD[15:0]

tv(BL_NE)

th(Data_NE)

Address

FMC_ A[25:16]

tv(A_NE)

FMC_NWE

t v(A_NE)

MS32755V1

Address

FMC_NADV

t v(NADV_NE)

tw(NADV)

tsu(Data_NE)

th(AD_NADV)

FMC_ NE

FMC_NOE

tw(NE)

tw(NOE)

tv(NOE_NE)

t h(NE_NOE)

th(A_NOE)

th(BL_NOE)

tsu(Data_NOE)

th(Data_NOE)

FMC_NWAIT

tsu(NWAIT_NE)

th(NE_NWAIT)

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Table 130. Asynchronous multiplexed PSRAM/NOR read timings

(1)

 

Symbol

Parameter

Min

Max

Unit

t

w(NE)

FMC_NE low time

3 × t

HCLK

 - 1

3 × t

HCLK

 + 1

ns

t

v(NOE_NE)

FMC_NEx low to FMC_NOE low

0

5

t

w(NOE)

FMC_NOE low time

2 × t

HCLK

 - 0.5

2 × t

HCLK

 + 0.5

t

h(NE_NOE)

FMC_NOE high to FMC_NE high hold time

t

HCLK

 -

t

v(A_NE)

FMC_NEx low to FMC_A valid

 -

1.5

t

v(NADV_NE)

FMC_NEx low to FMC_NADV low

0

1.5

t

w(NADV)

FMC_NADV low time

t

HCLK

 - 0.5

t

HCLK

 + 1

t

h(AD_NADV)

FMC_AD(address) valid hold time after FMC_NADV high)

t

HCLK

 - 4

 -

t

h(A_NOE)

Address hold time after FMC_NOE high

t

HCLK

 - 1

 -

t

su(Data_NE)

Data to FMC_NEx high setup time

t

HCLK

 + 15

 -

t

su(Data_NOE)

Data to FMC_NOE high setup time

15

 -

t

h(Data_NE)

Data hold time after FMC_NEx high

0

-

ns

t

h(Data_NOE)

Data hold time after FMC_NOE high

0

-

1. Evaluated by characterization. Not tested in production.

Table 131. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings

(1)

 

Symbol

Parameter

Min

Max

Unit

t

w(NE)

FMC_NE low time

8 × t

HCLK

 - 1

8 × t

HCLK

 + 1

ns

t

w(NOE)

FMC_NOE low time

7 × t

HCLK

 - 1

7 × t

HCLK

 + 1

t

su(NWAIT_NE)

FMC_NWAIT

(2)

 valid before FMC_NEx high

4 × t

HCLK

 + 9.5

-

t

h(NE_NWAIT)

FMC_NEx hold time after FMC_NWAIT invalid

3 ×  t

HCLK

 + 10

-

1. Evaluated by characterization. Not tested in production.

2. NWAIT pulse is equal to one HCLK cycle.

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Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms

          

NBL

Data

FMC_ NEx

FMC_ NBL[1:0]

FMC_ AD[15:0]

tv(BL_NE)

th(Data_NWE)

FMC_NOE

Address

FMC_ A[25:16]

tv(A_NE)

tw(NWE)

FMC_NWE

tv(NWE_NE)

t h(NE_NWE)

th(A_NWE)

th(BL_NWE)

t v(A_NE)

tw(NE)

MS32756V1

Address

FMC_NADV

t v(NADV_NE)

tw(NADV)

tv(Data_NADV)

th(AD_NADV)

FMC_NWAIT

tsu(NWAIT_NE)

th(NE_NWAIT)

Table 132. Asynchronous multiplexed PSRAM/NOR write timings

(1)

 

Symbol

Parameter

Min

Max

Unit

t

w(NE)

FMC_NE low time

3 × t

HCLK

 - 1

3 × t

HCLK

 + 1

ns

t

v(NWE_NE)

FMC_NEx low to FMC_NWE low

t

HCLK

 - 1

t

HCLK

t

w(NWE)

FMC_NWE low time

2 × t

HCLK

 - 0.5 2 × t

HCLK

 + 1

t

h(NE_NWE)

FMC_NWE high to FMC_NE high hold time

t

HCLK

-

t

v(A_NE)

FMC_NEx low to FMC_A valid

-

1

t

v(NADV_NE)

FMC_NEx low to FMC_NADV low

0

2

t

w(NADV)

FMC_NADV low time

t

HCLK

 - 0.5

t

HCLK

 + 1

t

h(AD_NADV)

FMC_AD(adress) valid hold time after FMC_NADV high)

t

HCLK

 - 4.5

-

t

h(A_NWE)

Address hold time after FMC_NWE high

t

HCLK

 - 0.5

-

t

h(BL_NWE)

FMC_BL hold time after FMC_NWE high

t

HCLK

 - 0.5

-

t

v(BL_NE)

FMC_NEx low to FMC_BL valid

 -

0.5

t

v(Data_NADV)

FMC_NADV high to Data valid

-

t

HCLK

 + 2

t

h(Data_NWE)

Data hold time after FMC_NWE high

t

HCLK

-

1. Evaluated by characterization. Not tested in production.

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Synchronous waveforms and timings

Figure 57

 to 

Figure 60

 represent synchronous waveforms an

Table 134

 to 

Table 137

 

provide the corresponding timings. The results shown in these tables are obtained with the 
following FMC configuration:

BurstAccessMode = FMC_BurstAccessMode_Enable

MemoryType = FMC_MemoryType_CRAM

WriteBurst = FMC_WriteBurst_Enable

CLKDivision = 1

DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

In all timing tables, the T

HCLK

 is the HCLK clock period.

Maximum FMC_CLK = 80 MHz for 2.7 V 

 V

DD

 

 3.6 V, with C

L

 = 15pF and 

with C

L

 = 20 pF

Maximum FMC_CLK = 80 MHz for 1.71 V 

 V

DD

 

 1.9 V with C

L

 = 15pF and 

with C

L

 = 20 pF

Table 133. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings

(1)

  

Symbol

Parameter

Min

Max

Unit

t

w(NE)

FMC_NE low time

8 × t

HCLK

 - 1

8 × t

HCLK

 + 1

ns

t

w(NWE)

FMC_NWE low time

6 × t

HCLK 

- 1

6 × t

HCLK 

+ 1

t

su(NWAIT_NE)

FMC_NWAIT valid before FMC_NEx high

5 × t

HCLK

 + 13

-

t

h(NE_NWAIT)

FMC_NEx hold time after FMC_NWAIT invalid

4 × t

HCLK

 + 12

-

1. Evaluated by characterization. Not tested in production.

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Figure 57. Synchronous multiplexed NOR/PSRAM read timings

          

FMC_CLK

FMC_NEx

FMC_NADV

FMC_A[25:16]

FMC_NOE

FMC_AD[15:0]

AD[15:0]

D1

D2

FMC_NWAIT

(WAITCFG = 1b, 
WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b, 
WAITPOL + 0b)

tw(CLK)

tw(CLK)

Data latency = 0

BUSTURN = 0

td(CLKL-NExL)

td(CLKH-NExH)

t d(CLKL-NADVL)

td(CLKL-AV)

td(CLKL-NADVH)

td(CLKH-AIV)

td(CLKL-NOEL)

td(CLKH-NOEH)

td(CLKL-ADV)

td(CLKL-ADIV)

tsu(ADV-CLKH)

th(CLKH-ADV)

tsu(ADV-CLKH)

th(CLKH-ADV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

MS32757V1

Table 134. Synchronous multiplexed NOR/PSRAM read timings

(1)(2)

 

Symbol

Parameter

Min

Max

Unit

t

w(CLK)

FMC_CLK period

2 × t

HCLK 

- 0.5

-

ns

t

d(CLKL-NExL)

FMC_CLK low to FMC_NEx low (x = 0..2)

-

1

t

d(CLKH_NExH)

FMC_CLK high to FMC_NEx high (x = 0..2)

t

HCLK 

- 0.5

-

t

d(CLKL-NADVL)

FMC_CLK low to FMC_NADV low

-

1.5

t

d(CLKL-NADVH)

FMC_CLK low to FMC_NADV high

1

-

t

d(CLKL-AV)

FMC_CLK low to FMC_Ax valid (x = 16..25)

-

2.5

t

d(CLKH-AIV)

FMC_CLK high to FMC_Ax invalid (x = 16..25)

t

HCLK 

- 0.5

-

t

d(CLKL-NOEL)

FMC_CLK low to FMC_NOE low

-

1.5

t

d(CLKH-NOEH)

FMC_CLK high to FMC_NOE high

t

HCLK 

+ 1

-

t

d(CLKL-ADV)

FMC_CLK low to FMC_AD[15:0] valid

-

2

t

d(CLKL-ADIV)

FMC_CLK low to FMC_AD[15:0] invalid

0

-

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DS13737 Rev 10

Figure 58. Synchronous multiplexed PSRAM write timings

          

t

su(ADV-CLKH)

FMC_A/D[15:0] valid data before FMC_CLK high

3

-

ns

t

h(CLKH-ADV)

FMC_A/D[15:0] valid data after FMC_CLK high

4

-

t

su(NWAIT-CLKH)

FMC_NWAIT valid before FMC_CLK high

1

-

t

h(CLKH-NWAIT)

FMC_NWAIT valid after FMC_CLK high

2.5

-

1. Evaluated by characterization. Not tested in production.

2. Clock ratio R = (HCLK period /FMC_CLK period).

Table 134. Synchronous multiplexed NOR/PSRAM read timings

(1)(2)

 (continued)

Symbol

Parameter

Min

Max

Unit

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Table 135. Synchronous multiplexed PSRAM write timings

(1)

 

Symbol

Parameter

Min

Max

Unit

t

w(CLK)

FMC_CLK period, 2.7 V 

 VDD 

 3.6 V

2 × t

HCLK

 - 0.5

 -

ns

t

d(CLKL-NExL)

FMC_CLK low to FMC_NEx low (x = 0..2)

 -

2

t

d(CLKH-NExH)

FMC_CLK high to FMC_NEx high (x = 0..2)

t

HCLK

 + 1.5

 -

t

d(CLKL-NADVL)

FMC_CLK low to FMC_NADV low

 -

2

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305

Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings

t

d(CLKL-NADVH)

FMC_CLK low to FMC_NADV high

1

 -

ns

t

d(CLKL-AV)

FMC_CLK low to FMC_Ax valid (x = 16..25)

 -

3

t

d(CLKH-AIV)

FMC_CLK high to FMC_Ax invalid (x = 16..25)

t

HCLK

 -

t

d(CLKL-NWEL)

FMC_CLK low to FMC_NWE low

 -

2.5

t

d(CLKH-NWEH)

FMC_CLK high to FMC_NWE high

t

HCLK

 + 1

 -

t

d(CLKL-ADV)

FMC_CLK low to FMC_AD[15:0] valid

 -

2

t

d(CLKL-ADIV)

FMC_CLK low to FMC_AD[15:0] invalid

0

 -

t

d(CLKL-DATA)

FMC_A/D[15:0] valid data after FMC_CLK low

 -

3

t

d(CLKL-NBLL)

FMC_CLK low to FMC_NBL low

-

2

t

d(CLKH-NBLH)

FMC_CLK high to FMC_NBL high

t

HCLK

 + 0.5

-

t

su(NWAIT-CLKH)

FMC_NWAIT valid before FMC_CLK high

3

-

t

h(CLKH-NWAIT)

FMC_NWAIT valid after FMC_CLK high

2.5

-

1. Evaluated by characterization. Not tested in production.

Table 135. Synchronous multiplexed PSRAM write timings

(1)

 (continued)

Symbol

Parameter

Min

Max

Unit

FMC_CLK

FMC_NEx

FMC_A[25:0]

FMC_NOE

FMC_D[15:0]

D1

D2

FMC_NWAIT

(WAITCFG = 1b, 
WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b, 
WAITPOL + 0b)

tw(CLK)

tw(CLK)

Data latency = 0

td(CLKL-NExL)

td(CLKH-NExH)

td(CLKL-AV)

td(CLKH-AIV)

td(CLKL-NOEL)

td(CLKH-NOEH)

tsu(DV-CLKH)

th(CLKH-DV)

tsu(DV-CLKH)

th(CLKH-DV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

t h(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

MS32759V1

FMC_NADV

td(CLKL-NADVL)

td(CLKL-NADVH)

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DS13737 Rev 10

          

Figure 60. Synchronous non-multiplexed PSRAM write timings

Table 136. Synchronous non-multiplexed NOR/PSRAM read timings

(1)

 

Symbol

Parameter

Min

Max

Unit

t

w(CLK)

FMC_CLK period

t

HCLK

 - 

0.5

-

ns

t

d(CLKL-NExL)

FMC_CLK low to FMC_NEx low (x = 0..2)

-

1

t

d(CLKH-NExH)

FMC_CLK high to FMC_NEx high (x = 0…2)

t

HCLK 

- 0.5

-

t

d(CLKL-NADVL)

FMC_CLK low to FMC_NADV low

-

1.5

t

d(CLKL-NADVH)

FMC_CLK low to FMC_NADV high

1

-

t

d(CLKL-AV)

FMC_CLK low to FMC_Ax valid (x = 0…25)

-

2.5

t

d(CLKH-AIV)

FMC_CLK high to FMC_Ax invalid (x = 0…25)

t

HCLK

 - 0

.5

-

t

d(CLKL-NOEL)

FMC_CLK low to FMC_NOE low

-

1.5

t

d(CLKH-NOEH)

FMC_CLK high to FMC_NOE high

t

HCLK 

+ 1

-

t

su(DV-CLKH)

FMC_D[15:0] valid data before FMC_CLK high

3

-

t

h(CLKH-DV)

FMC_D[15:0] valid data after FMC_CLK high

4

-

t

su(NWAIT-CLKH)

FMC_NWAIT valid before FMC_CLK high

1

-

t

h(CLKH-NWAIT)

FMC_NWAIT valid after FMC_CLK high

2.5

-

1. Evaluated by characterization. Not tested in production.

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W

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W

G&/./1$'9+

W

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)0&B1%/

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G&/.+1%/+

STM32U575RGT6-html.html

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STM32U575xx

Electrical characteristics

305

          

NAND controller waveforms and timings

Figure 61

 to 

Figure 64

 represent synchronous waveforms, and 

Table 138

/

Table 139

 provide 

the corresponding timings. The results shown in these tables are obtained with the following 
FMC configuration:

COM.FMC_SetupTime = 0x01

COM.FMC_WaitSetupTime = 0x03

COM.FMC_HoldSetupTime = 0x02

COM.FMC_HiZSetupTime = 0x01

ATT.FMC_SetupTime = 0x01

ATT.FMC_WaitSetupTime = 0x03

ATT.FMC_HoldSetupTime = 0x02

ATT.FMC_HiZSetupTime = 0x01

Bank = FMC_Bank_NAND

MemoryDataWidth = FMC_MemoryDataWidth_16b

ECC = FMC_ECC_Enable

ECCPageSize = FMC_ECCPageSize_512Bytes

TCLRSetupTime = 0

TARSetupTime = 0

In all timing tables, the T

HCLK

 is the HCLK clock period.

Table 137. Synchronous non-multiplexed PSRAM write timings

(1)

 

Symbol

Parameter

Min

Max

Unit

t

w(CLK)

FMC_CLK period

2 × t

HCLK

 - 

0.5

-

ns

t

d(CLKL-NExL)

FMC_CLK low to FMC_NEx low (x = 0..2)

-

3

t

d(CLKH-NExH)

FMC_CLK high to FMC_NEx high (x = 0..2)

t

HCLK

 + 

1.5

-

t

d(CLKL-NADVL)

FMC_CLK low to FMC_NADV low

-

2

t

d(CLKL-NADVH)

FMC_CLK low to FMC_NADV high

1

-

t

d(CLKL-AV)

FMC_CLK low to FMC_Ax valid (x = 16..25)

-

3

t

d(CLKH-AIV)

FMC_CLK high to FMC_Ax invalid (x = 16..25)

t

HCLK

-

t

d(CLKL-NWEL)

FMC_CLK low to FMC_NWE low

-

2.5

t

d(CLKH-NWEH)

FMC_CLK high to FMC_NWE high

t

HCLK

 + 

1

-

t

d(CLKL-Data)

FMC_D[15:0] valid data after FMC_CLK low

-

3

t

d(CLKL-NBLL)

FMC_CLK low to FMC_NBL low

-

2

t

d(CLKH-NBLH)

FMC_CLK high to FMC_NBL high

t

HCLK

 + 

0.5

-

t

su(NWAIT-CLKH)

FMC_NWAIT valid before FMC_CLK high

3

-

t

h(CLKH-NWAIT)

FMC_NWAIT valid after FMC_CLK high

2.5

-

1. Evaluated by characterization. Not tested in production.

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DS13737 Rev 10

Figure 61. NAND controller waveforms for read access

1. y = 7 or 15 depending on the NAND flash memory interface.

Figure 62. NAND controller waveforms for write access

1. y = 7 or 15 depending on the NAND flash memory interface.

MSv73150V1

FMC_NWE

FMC_NOE (NRE)

FMC_D[y:0]

t

w(NOE)

t

su(D-NOE)

t

h(NOE-D)

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NCEx

t

d(ALE-NOE)

t

h(NOE-ALE)

MSv73151V1

t

w(NWE)

t

h(NWE-D)

t

v(NWE-D)

FMC_NWE

FMC_NOE (NRE)

FMC_D[y:0]

t

d(D-NWE)

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NCEx

t

d(ALE-NWE)

t

h(NWE-ALE)

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305

Figure 63. NAND controller waveforms for common memory read access

Figure 64. NAND controller waveforms for common memory write access

          

MSv38005V1

FMC_NWE

FMC_NOE

FMC_D[15:0]

t

w(NOE)

t

su(D-NOE)

t

h(NOE-D)

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NCEx

t

d(NCE-NOE)

t

h(NOE-ALE)

MSv38006V1

t

w(NWE)

t

h(NWE-D)

t

v(NWE-D)

FMC_NWE

FMC_NOE

FMC_D[15:0]

t

d(D-NWE)

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NCEx

t

d(NCE-NWE)

t

h(NOE-ALE)

Table 138. Switching characteristics for NAND Flash read cycles

(1)

 

Symbol Parameter  Min

Max

Unit 

t

w(NOE)

FMC_NOE low width

4 × t

HCLK

 - 0.5

4 ×  t

HCLK

 + 0.5

ns

t

su(D-NOE)

FMC_D[15-0] valid data before FMC_NOE high

10

-

t

h(NOE-D)

FMC_D[15-0] valid data after FMC_NOE high

0

-

t

d(ALE-NOE)

FMC_ALE valid before FMC_NOE low

-

3 × t

HCLK

 + 0.5

t

h(NOE-ALE)

FMC_NWE high to FMC_ALE invalid

4 × t

HCLK

 - 1

-

1. Evaluated by characterization. Not tested in production.

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DS13737 Rev 10

          

5.3.34 OCTOSPI 

characteristics

Unless otherwise specified, the parameters given in 

Table 140

 to

Table 142

 are derived from 

tests performed under the ambient temperature, f

AHB

 frequency and V

DD

 supply voltage 

conditions summarized in 

Table 32

, with the following configuration:

Output speed set to OSPEEDRy[1:0] = 10

Delay block enabled for DTR (with DQS)/HyperBus

Measurement points done at 0.5

 × 

V

DD

 level

I/O compensation cell activated

HSLV activated when V

DD

 

 2.7 V

Voltage scaling range 1 unless otherwise specified

Refer to 

Section 5.3.15: I/O port characteristics

 for more details on the input/output alternate 

function characteristics.

           

Table 139. Switching characteristics for NAND Flash write cycles

(1)

 

Symbol Parameter  Min

Max

Unit 

t

w(NWE)

FMC_NWE low width

4 × t

HCLK

 - 0.5

4 × t

HCLK

 + 0.5

ns

t

v(NWE-D)

FMC_NWE low to FMC_D[15-0] valid

0

-

t

h(NWE-D)

FMC_NWE high to FMC_D[15-0] invalid

2 × t

HCLK

 + 1

-

t

d(D-NWE)

FMC_D[15-0] valid before FMC_NWE high

5 × t

HCLK

 - 5

-

t

d(ALE_NWE)

FMC_ALE valid before FMC_NWE low

-

3 × t

HCLK

 + 0.5

t

h(NWE-ALE)

FMC_NWE high to FMC_ALE invalid

2 × t

HCLK

 - 0.5

-

1. Evaluated by characterization. Not tested in production.

Table 140. OCTOSPI characteristics in SDR mode

(1)(2)(3)

 

Symbol

Parameter

 Conditions

Min

Typ

Max

Unit

f

(CLK)

OCTOSPI clock 
frequency

1.71 V 

 V

DD

 

 3.6 V 

Voltage range 1

 

C

L

 = 15 pF

-

-

93

MHz

2.7 V 

 V

DD

 

 3.6 V

 

Voltage range1

 

C

L

 = 15 pF

-

-

100

1.71 V 

 V

DD

 

 3.6 V

 

Voltage range 4

 

C

L

 = 15 pF

-

-

24

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305

          

t

w(CLKH)

OCTOSPI clock high 
and low time

 

(even division)

PRESCALER[7:0] = n 
(n = 0, 1, 3, 5,..255)

t

(CLK)

/2 - 0.5

-

t

(CLK)

/2

ns

t

w(CLKL)

t

(CLK)

/2 - 0.5

-

t

(CLK)

/2

t

w(CLKH)

OCTOSPI clock high 
and low time

 

(odd division)

PRESCALER[7:0] = n
(n = 2, 4, 6,..254)

(n/2) × t

(CLK)

/(n+1) - 0.5

-

(n/2) × t

(CLK)

/(n+1)

t

w(CLKL)

((n/2)+1) × t

(CLK)

/(n+1) - 0.5

-

((n/2)+1) × t

(CLK)

/(n+1)

t

s(IN)

Data input setup time

Voltage range 1

2.75

-

-

Voltage range 4

3

-

-

t

h(IN)

Data input hold time

Voltage range 1

0.5

-

-

Voltage range 4

1

-

-

t

v(OUT)

Data output valid time

Voltage range 1

-

0.5

1

Voltage range 4

-

1.5

2.5

t

h(OUT)

Data output hold time

Voltage range 1

0.5

-

-

Voltage range 4

-0.25

-

-

1. Evaluated by characterization. Not tested in production.

2. Measured values in this table apply to Octo- and Quad-SPI data modes.

3. Delay block bypassed.

Table 140. OCTOSPI characteristics in SDR mode

(1)(2)(3)

 (continued)

Symbol

Parameter

 Conditions

Min

Typ

Max

Unit

Table 141. OCTOSPI characteristics in DTR mode (no DQS)

(1)(2)(3)

 

Sym

bol

Parameter

 Conditions

Min

Typ

Max

Unit

f

(CLK)

OCTOSPI clock 
frequency

1.71 V 

 V

DD

 

 3.6 V Voltage 

range 1, C

L

 = 15 pF

-

-

93

(4)

MHz

2.7 V 

 V

DD

 

 3.6 V

 

Voltage range1, C

L

 = 15 pF

-

-

100

(4)

1.71 V 

 V

DD

 

 3.6 V

 

Voltage range 4, C

L

 = 15 pF

-

-

24

(4)

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DS13737 Rev 10

          

t

w(CLKH)

OCTOSPI clock 
high and low time 
(even division)

PRESCALER[7:0] = n 
(n = 0, 1, 3, 5,..255)

t

(CLK)

/2 - 0.5

-

t

(CLK)

/2 + 0.5

ns

t

w(CLKL)

t

(CLK)

/2 - 0.5

-

t

(CLK)

/2 + 0.5

t

w(CLKH)

OCTOSPI clock 
high and low time 
(odd division)

PRESCALER[7:0] = n 

 

(n = 2, 4, 6,..254)

(n/2) × t

(CLK)

/(n+1) - 0.5

-

(n/2) × t

(CLK)

/(n+1) + 0.5

t

w(CLKL)

((n/2)+1) × t

(CLK)

/(n+1) - 0.5

-

((n/2)+1) × t

(CLK)

/(n+1) + 0.5

t

sr(IN) 

t

sf(IN)

Data input setup 
time

Voltage range 1

3.25

-

-

Voltage range 4

3.75

-

-

t

hr(IN) 

t

hf(IN)

Data input hold 
time

Voltage range 1

1

-

-

Voltage range 4

1.5

-

-

t

vr(OUT)

t

vf(OUT)

Data output valid 
time, DHQC = 0

Voltage range 1

-

6

9.25

Voltage range 4

-

13.25

19.75

Data output valid 
time, DHQC = 1

Voltage range 1

 

All prescaler values (except 0)

-

t

(CLK)

/4

 + 0.75

t

(CLK)

/4 + 1.5

t

hr(OUT)

t

hf(OUT)

Data output hold 
time DHQC = 0

Voltage range 1

4

-

-

Voltage range 4

8

-

-

Data output hold 
time DHQC = 1

Voltage range 1

 

All prescaler values (except 0)

t

(CLK)

/4 - 0.5

-

-

1. Evaluated by characterization. Not tested in production.

2. Measured values in this table apply to Octo- and Quad-SPI data modes.

3. Delay block bypassed.

4. Activating DHQC is mandatory to reach this frequency.

Table 141. OCTOSPI characteristics in DTR mode (no DQS)

(1)(2)(3)

 (continued)

Sym

bol

Parameter

 Conditions

Min

Typ

Max

Unit

Table 142. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus

(1)(2)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f

(CLK)

OCTOSPI clock 
frequency

1.71 V 

 V

DD

 

 3.6 V 

Voltage range 1 
C

L

 = 15 pF

-

-

93

(3)(4)

MHz

2.7 V 

 V

DD

 

 3.6 V 

Voltage range1 
C

L

 = 15 pF

-

-

100

(3)(4)

1.71 V 

 V

DD

 

 3.6 V 

Voltage range 4 
C

L

 = 15 pF

-

-

24

(4)

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305

t

w(CLKH)

OCTOSPI clock 
high and low time 
(even division)

PRESCALER[7:0] = n 
(n = 0, 1, 3, 5,..255)

t

(CLK)

/2 - 0.5

-

t

(CLK)

/2 + 0.5

ns

t

w(CLKL)

t

(CLK)

/2 - 0.5

-

t

(CLK)

/2 + 0.5

t

w(CLKH)

OCTOSPI clock 
high and low time 
(odd division)

PRESCALER[7:0] = n

 

(n = 2, 4, 6,..254)

(n/2) × t

(CLK)

/(n+1) - 0.5

-

(n/2) × t

(CLK)

/(n+1) + 0.5

t

w(CLKL)

((n/2)+1) × t

(CLK)

/(n+1) - 0.5

-

((n/2)+1) × t

(CLK)

/(n+1) + 0.5

t

v(CLK)

Clock valid time

-

-

-

t

(CLK)

 + 2

t

h(CLK)

Clock hold time

-

t

(CLK)

/2 - 0.5

-

-

V

ODr(

CLK)

(5)

CLK, NCLK 
crossing level on 
CLK rising edge

V

DD

 = 1.8 V

975

-

1120

mV

V

ODf(

CLK)

(5)

CLK, NCLK 
crossing level on 
CLK falling edge

V

DD

 = 1.8 V

845

-

990

t

w(CS)

Chip select high 
time

-

3  ×  t

(CLK)

-

-

ns

t

v(DQ)

Data input valid 
time

-

0

-

-

t

v(DS)

Data strobe input 
valid time

0

-

-

t

h(DS)

Data strobe input 
hold time

-

0

-

-

t

v(RWDS)

Data strobe output 
valid time

-

-

-

3  ×    t

(CLK)

t

sr(DQ) 

t

sf(DQ)

Data input setup 
time

Voltage range 1

-0.5

-

t

(CLK)

/2 - 1.5

(6)

Voltage range 4

-0.25

-

t

(CLK)

/2 - 1.75

(6)

t

hr(DQ) 

t

hf(DQ)

Data input hold 
time

Voltage range 1

1.5

-

-

Voltage range 4

1.75

-

-

t

vr(OUT) 

t

vf(OUT)

Data output valid 
time DHQC = 0

Voltage range 1

-

6

9.5

ns

Voltage range 4

-

13

19.5

Data output valid 
time DHQC = 1

Voltage range 1

 

All prescaler values 
(except 0)

-

t

(CLK)

/4 + 0.5

t

(CLK)

/4 + 1.25

t

hr(OUT) 

t

hf(OUT)

Data output hold 
time DHQC = 0

Voltage range 1

4

-

-

Voltage range 4

7.75

-

-

t

hr(OUT)

Data output hold 
time DHQC = 1

Voltage range 1

 

All prescaler values 
(except 0)

t

(CLK)

/4 - 0.5

-

-

1. Evaluated by characterization. Not tested in production.

2. Delay block activated.

Table 142. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus

(1)(2)

 (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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DS13737 Rev 10

Figure 65. OCTOSPI timing diagram - SDR mode

Figure 66. OCTOSPI timing diagram - DDR mode

Figure 67. OCTOSPI HyperBus clock

3. Maximum frequency values are given for a RWDS to DQ skew of maximum ±1.0 ns. 

4. Activating DHQC is mandatory to reach this frequency.

5. Crossing results are in line with specification, except for PA3/PB5 CLK that exceed slightly the specification.

6. Data input maximum setup time does not take into account the data level switching duration.

MSv36878V3

Data output

D0

D1

D2

Clock

Data input

D0

D1

D2

t

(CLK)

t

w(CLKH)

t

w(CLKL)

t

r(CLK)

t

f(CLK)

t

s(IN)

t

h(IN)

t

v(OUT)

t

h(OUT)

MSv36879V4

Data output

D0

D2

D4

Clock

Data input

D0

D2

D4

t

(CLK)

t

w(CLKH)

t

w(CLKL)

t

r(CLK)

t

f(CLK)

t

sf(IN)

t

hf(IN)

t

vf(OUT)

t

hr(OUT)

D1

D3

D5

D1

D3

D5

t

vr(OUT)

t

hf(OUT)

t

sr(IN)

t

hr(IN)

MSv47732V3

CLK

t

(NCLK)

t

w(NCLKL)

t

w(NCLKH)

t

f(NCLK)

t

r(NCLK)

t

r(CLK)

t

w(CLKH)

t

w(CLKL)

t

(CLK)

t

f(CLK)

NCLK

V

OD(CLK)

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Figure 68. OCTOSPI HyperBus read

Figure 69. OCTOSPI HyperBus read with double latency

Figure 70. OCTOSPI HyperBus write

MSv47733V3

NCS

t  

ACC  

= Initial access

Latency count

Command address

47:40 39:32

31:24

23:16

15:8

7:0

Dn

A

Dn

B

Dn+1

A

Dn+1

B

Host drives DQ[7:0] and the memory drives RWDS.

CLK, NCLK

RWDS

DQ[7:0]

Memory drives DQ[7:0] and RWDS.

t

w(CS)

t

v(RWDS)

t

v(CLK)

t

v(DS)

t

v(DQ)

t

h(CLK)

t

h(DS)

t

v(OUT)

t

h(OUT)

t

h(DQ)

t

s(DQ)

MSv49351V3

NCS

t

RWR

=Read/write recovery

t

ACC

 = Access

Additional latency

Command address

47:40 39:32 31:24 23:16 15:8

7:0

High = 2x latency count

Low = 1x latency count

Dn

A

Dn

B

Dn+1

A

Dn+1

B

Host drives DQ[7:0] and the memory drives RWDS.

RWDS and data
are edge aligned

CLK, NCLK

RWDS

DQ[7:0]

Memory drives DQ[7:0] and RWDS.

t

CKDS

MSv47734V3

NCS

Access latency

Latency count

Command address

47:40

39:32

31:24

23:16

15:8

7:0

Dn

A

Dn

B

Dn+1

A

Dn+1

B

Host drives DQ[7:0] and the memory drives RWDS.

Host drives DQ[7:0] and RWDS.

CLK, NCLK

RWDS

DQ[7:0]

t

w(CS)

t

v(RWDS)

t

v(CLK)

t

h(CLK)

High = 2x latency count
Low = 1x latency count

Read write recovery

t

h(OUT)

t

v(OUT)

t

h(OUT)

t

v(OUT)

t

h(OUT)

t

v(OUT)

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5.3.35 SD/SDIO/

e

•MMC card host interfaces (SDMMC) characteristics

Unless otherwise specified, the parameters given in 

Table 143

 an

Table 144

 are derived 

from tests performed under the ambient temperature, f

AHB

 frequency and V

DD

 supply 

voltage conditions summarized in 

Table 32

, with the following configuration:

Output speed set to OSPEEDRy[1:0] = 10

Capacitive load C

L

 = 30 pF, unless otherwise specified

Measurement points done at 0.5

 × 

V

DD

 level

I/O compensation cell activated 

HSLV activated when V

DD

 

 2.7 V 

Voltage scaling range 1

Refer to 

Section 5.3.15: I/O port characteristics

 for more details on the input/output 

characteristics.

          

Table 143. SD/

e

•MMC characteristics (V

DD

 = 2.7 V to 3.6 V)

(1)(2)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f

PP

Clock frequency in data transfer mode

-

0

-

100

(3)

MHz

t

W(CKL)

Clock low time

f

PP

 = 52 MHz

8.5

9.5

-

ns

t

W(CKH)

Clock high time

f

PP

 = 52 MHz

8.5

9.5

-

CMD, D inputs (referenced to CK) in 

e

•MMC legacy/SDR/DDR and SD HS/SDR

(4)

/DDR

(4)

 modes

t

ISU

Input setup time HS

-

3.5

-

-

ns

t

IH

Input hold time HS

-

1.5

-

-

t

IDW

(5)

Input valid window (variable window)

-

4.5

-

-

CMD, D outputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR

(4)

/DDR

(4)

 modes

t

OV

Output valid time HS

-

-

5.5

6

ns

t

OH

Output hold time HS

-

4

-

-

CMD, D inputs (referenced to CK) in SD default mode

t

ISU

Input setup time SD

-

3.5

-

-

ns

t

IH

Input hold time SD

-

1.5

-

-

CMD, D outputs (referenced to CK) in SD default mode

t

OV

Output valid default time SD

-

-

0.5

2

ns

t

OH

Output hold default time SD

-

0

-

-

1. Evaluated by characterization. Not tested in production.

2. For SDMMC2 in SD/

e

.MMC DDR mode, the clock OSPEEDRy[1:0] is set to 01 while data OSPEEDRy[1:0] remains at 10.

3. With capacitive load C

L

 = 20 pF.

4. For SD 1.8 V support, an external voltage converter is needed.

5. Minimum window of time where the data needs to be stable for proper sampling in tuning mode.

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Figure 71. SD high-speed mode

Figure 72. SD default mode

Table 144. 

e

•MMC characteristics (V

DD

 = 1.71 V to 1.9 V)

(1)(2)

 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f

PP

Clock frequency in data transfer mode

All modes 
except DDR

-

-

84

MHz

DDR mode

-

-

40

(3)

t

W(CKL)

Clock low time

f

PP

 = 52 MHz

8.5

9.5

-

ns

t

W(CKH)

Clock high time

f

PP

 = 52 MHz

8.5

9.5

-

CMD, D inputs (referenced to CK) in 

e

•MMC mode

t

ISU

Input setup time HS

-

2.5

-

-

ns

t

IH

Input hold time HS

-

2

-

-

t

IDW

(4)

Input valid window (variable window)

-

4

-

-

CMD, D outputs (referenced to CK) in 

e

•MMC mode

t

OV

Output valid time HS

-

-

10.5

13/15

(5)

ns

t

OH

Output hold time HS

-

7

-

-

1. Evaluated by characterization. Not tested in production.

2. With capacitive load C

L

 = 20 pF.

3. For DDR mode, the maximum frequency is 40 MHz and HSLV must be OFF.

4. Minimum window of time where the data needs to be stable for proper sampling in tuning mode.

5. t

OV

 = 13 ns for SDMMC1 and t

OV

 = 15 ns for SDMMC2.

MSv69709V1

CK

D, CMD output

D, CMD input

t

OV

t

OH

t

ISU

t

IH

t

C(CK)

t

W(CKH)

t

W(CKL)

MSv69710V1

CK

D, CMD output

t

OV

t

OH

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DS13737 Rev 10

Figure 73. SDMMC DDR mode

5.3.36 Delay 

block 

characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests 
performed under the ambient temperature, f

HCLK

 frequency and V

DD

 supply voltage 

conditions summarized in 

Table 32

.

          

5.3.37 I

2

C interface characteristics

The I

2

C interface meets the timings requirements of the I

2

C-bus specification and user 

manual rev. 03 for: 

Standard-mode (Sm): with a bitrate up to 100 Kbit/s

Fast-mode (Fm): with a bitrate up to 400 Kbit/s

Fast-mode Plus (Fm+): with a bitrate up to 1 Mbit/s

The I2C timings requirements are specified by design, not tested in production, when the 
I2C peripheral is properly configured (refer to the product reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and 
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS 
connected between the I/O pin and V

DDIOx

 is disabled, but is still present. Only FT_f I/O pins 

support Fm+ low-level output-current maximum requirement. Refer to 

Section 5.3.15: I/O 

port characteristics

 for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog 
filter characteristics.

MSv69158V1

CK

D output

t

OV

t

OH

t

ISU

t

IH

D input

t

OV

t

OH

Valid data

t

ISU

t

IH

Valid data

Valid data

Valid data

t

W(CKH)

t

W(CKL)

Table 145. Delay block characteristics

(1)

 

Symbol

Parameter

 Conditions

Min

Typ 

Max

Unit

t

init

Initial delay

-

900

1300

2100

ps

t

Unit delay

-

34

41

51

1. Evaluated by characterization. Not tested in production.

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305

          

5.3.38 USART 

(SPI 

mode) characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests 
performed under the ambient temperature, f

PCLKx

 frequency and V

DD

 supply voltage 

conditions summarized in 

Table 32

, with the following configuration:

Output speed set to OSPEEDRy[1:0] = 10

Capacitive load C

L

 = 30pF

Measurement points done at 0.5

 × 

V

DD

 level

I/O compensation cell activated

HSLV activated when V

DD

 

 2.7 V

Voltage scaling range 1

Refer to 

Section 5.3.15: I/O port characteristics

 for more details on the input/output alternate 

function characteristics (NSS, CK, TX, RX for USART).

          

Table 146. I2C analog filter characteristics

(1)

 

Symbol

Parameter

Min

Max

Unit

t

AF

Maximum pulse width of spikes that are suppressed by the analog filter

50

(2)

115

(3)

ns

1. Specified by design. Not tested in production.

2. Spikes with widths below t

AF

 min are filtered.

3. Spikes with width above t

AF

 max are not filtered.

Table 147. USART (SPI mode) characteristics

(1)

 

Symbol

Parameter

 Conditions

Min

Typ

Max

Unit

f

CK

USART clock 
frequency

SPI master mode, 1.71 V 

 V

DDIOX

 3.6 V

-

-

20

MH

z

SPI slave receiver,

 

1.71 V 

 V

DDIOX

 3.6 V

-

-

53

SPI slave transmitter,

 

1.71 V 

 V

DDIOX

 

 3.6 V

-

-

28.5

SPI slave transmitter,

 

2.7 V 

 V

DDIOX

 

 3.6 V

-

-

32

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DS13737 Rev 10

Figure 74. USART timing diagram in SPI master mode

t

su(NSS)

NSS setup time SPI slave mode

T

ker

(2)

 

+ 2

-

-

ns

t

h(NSS)

NSS hold time

SPI slave mode

2

-

-

t

w(CKH)

t

w(CKL)

CK high and low 
time

SPI master mode

1/f

CK

 / 2 - 1 1/f

CK

 / 2 1/f

CK

 / 2 + 1

t

su(RX)

Data input setup 
time

SPI master mode

14

-

-

SPI slave mode

1

-

-

t

h(RX)

Data input hold 
time

SPI master mode

4

-

-

t

h(RX)

SPI slave mode

1

-

-

t

v(TX)

Data output 
valid time

SPI slave mode, 2.7 V 

 V

DDIOX

 

 3.6 V

-

11

15.5

SPI slave mode, 1.71 V 

 V

DDIOX

 

 3.6 V

-

11

17.5

t

v(TX)

SPI master mode 

-

2.5

6.5

t

h(TX)

Data output hold 
time

SPI slave mode

8.5

-

-

t

h(TX)

SPI master mode 

2

-

-

1. Evaluated by characterization. Not tested in production.

2. T

ker

 is the usart_ker_ck_pres clock period.

Table 147. USART (SPI mode) characteristics

(1)

 (continued)

Symbol

Parameter

 Conditions

Min

Typ

Max

Unit

MSv65386V6

1/f

CK

t

w(CKH)

t

w(CKL)

CPHA=0
CPOL=0

CPHA=0
CPOL=1

TX output

RX input

CK output

MSB 

OUT

LSB OUT

BIT1 OUT

MSB 

IN

LSB IN

BIT6 IN

CPHA=1
CPOL=0

CPHA=1
CPOL=1

CK output

t

su(RX)

t

v(TX)

t

h(TX)

t

h(RX)

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305

Figure 75. USART timing diagram in SPI slave mode

5.3.39 SPI 

characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests 
performed under the ambient temperature, f

PCLKx 

frequency and supply voltage conditions 

summarized in 

Table 32

.

Output speed set to OSPEEDRy[1:0] = 10

Capacitive load C

L

 = 30 pF

Measurement points done at 0.5

 × 

V

DD

 level

I/O compensation cell activated

HSLV activated when V

DD

 

 2.7 V 

Refer to 

Section 5.3.15: I/O port characteristics

 for more details on the input/output alternate 

function characteristics (NSS, SCK, MOSI, MISO for SPI).

MSv65387V6

NSS input

CPHA=0

CPOL=0

CK input

CPHA=0

CPOL=1

TX output

RX input

t

h(RX)

t

w(CKL)

t

w(CKH)

1/f

CK

t

h(NSS)

t

su(NSS)

t

v(TX)

Next bits IN

Last bit OUT

First bit IN

First bit OUT

Next bits OUT

t

h(TX)

Last bit IN

t

su(RX)

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Table 148. SPI characteristics

(1)

 

Symbol

Parameter

 Conditions

Min

Typ

Max

Unit

f

SCK

1/t

c(SCK)

SPI clock frequency

Master mode, 2.7 V 

 V

DDIOX

 

 3.6 V, 

 

voltage range 1

-

-

80

MHz

Master mode, 1.71 V 

 V

DDIOX

 < 2.7 V

 

voltage range 1

-

-

75

or 50

(2)

Master transmitter mode, 
2.7 V 

 V

DDIOX

 

 3.6 V, 

 

voltage range 1

-

-

80

Master transmitter mode, 
1.71 V 

 V

DDIOX

 

 2.7 V, 

 

voltage range 1

-

-

75

or 50

(2)

Slave receiver mode, 
1.71 V 

 V

DDIOX

 

 3.6 V, 

 

voltage range 1

-

-

100

Slave mode transmitter/full duplex

(3)

,

 

1.71 V 

 V

DDIOX

 < 2.7 V, 

 

voltage range 1

-

-

41.5

or 25.5

(4)

Slave mode transmitter/full duplex

(3)

,

 

2.7 V 

 V

DDIOX

 

 3.6 V, 

 

voltage range 1

-

-

38.5

Master or slave mode 
1.71 V 

 V

DDIOX

 

 3.6 V, 

 

voltage range 4

-

-

12.5

Master or slave mode 
1.08 V 

 V

DDIO2

 

 1.32 V

(5)

-

-

15

t

su(NSS)

NSS setup time

Slave mode

4

-

-

ns

t

h(NSS)

NSS hold time

Slave mode

3

-

-

t

w(SCKH)

t

w(SCKL)

SCK high and low time Master mode 

t

SCK

(6)

/2 - 1 t

SCK

/2 t

SCK

/2 + 1

t

su(MI)

Data input setup time

Master mode

4.5

-

-

t

su(SI)

Slave mode

2.5

-

-

t

h(MI)

Data input hold time

Master mode

3

-

-

t

h(SI)

Slave mode

1

-

-

t

a(SO)

Data output access 
time

Slave mode

9

-

34

t

dis(SO)

Data output disable 
time

Slave mode

9

-

16

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t

v(SO)

Data output valid time

Slave mode, 2.7 V 

 V

DDIOX

 

 3.6 V,

 

voltage range 1

-

10

13

ns

Slave mode, 1.71 V 

 V

DDIOX

 < 2.7 V,

 

voltage range 1

-

10

12

or 19.5

(4)

Slave mode, 1.71 V 

 V

DDIOX

 

 3.6 V, 

 

voltage range 4

-

17

19.5

or 27

(4)

Slave mode, 
1.08 V 

 V

DDIO2

 

 1.32 V

(5)

-

21

22.5

t

v(MO)

Master mode 

-

1.5

2 or 9.5

(7)

or 12.5

(8)

t

h(SO)

Data output hold time

Slave mode, 1.71 V 

 V

DDIOX

 

 3.6 V

7

-

-

Slave mode, 
1.08 V 

 V

DDIO2

 

 1.32 V

(5)

18

-

-

t

h(MO)

Master mode 

0

-

-

1. Evaluated by characterization. Not tested in production.

2. When using PA5, PA9, PC10, PB3, PB13. 

3. The maximum frequency in slave transmitter mode is determined by the sum of t

v(SO)

 and t

su(MI)

 that has to fit into SCK low 

or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master 

having t

su(MI)

 = 0 while Duty(SCK) = 50%.

4. When using PA11, PB4, PB14.

5. The SPI is mapped on port G I/Os, that is supplied by VDDIO2 specified down to 1.08V. The SPI is tested at this value.

6. t

SCK

 = tspi_ker_ck

 × 

baud rate prescaler.

7. When using PA12. 

8. When using PB15.

Table 148. SPI characteristics

(1)

 (continued)

Symbol

Parameter

 Conditions

Min

Typ

Max

Unit

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Figure 76. SPI timing diagram - slave mode and CPHA = 0

Figure 77. SPI timing diagram - slave mode and CPHA = 1

MSv41658V2

NSS input

CPHA=0

CPOL=0

SCK input

CPHA=0

CPOL=1

MISO output

MOSI input

t

su(SI)

t

h(SI)

t

w(SCKL)

t

w(SCKH)

t

c(SCK)

t

h(NSS)

t

dis(SO)

t

su(NSS)

t

a(SO)

t

v(SO)

Next bits IN

Last bit OUT

First bit IN

First bit OUT

Next bits OUT

t

h(SO)

Last bit IN

MSv41659V2

t

h(SI)

t

c(SCK)

t

w(SCKH)

t

w(SCKL)

t

su(NSS)

t

a(SO)

t

v(SO)

t

h(NSS)

t

dis(SO)

t

su(SI)

NSS input

CPHA=1
CPOL=0

CPHA=1
CPOL=1

MISO output

MOSI input

SCK input

First bit OUT

Next bits OUT

Last bit OUT

First bit IN

Last bit IN

Next bits IN

t

h(SO)

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305

Figure 78. SPI timing diagram - master mode

5.3.40 SAI 

characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests 
performed under the ambient temperature, f

PCLKx

 frequency and V

DD

 supply voltage 

conditions summarized in

Table 32

, with the following configuration:

Output speed set to OSPEEDRy[1:0] = 10

Capacitive load C

L

 = 30 pF

Measurement points done at 0.5

 × 

V

DD

 level

I/O compensation cell activated

HSLV activated when V

DD

 

 2.7 V

Voltage scaling range 1

Refer to 

Section 5.3.15: I/O port characteristics

 for more details on the input/output alternate 

function characteristics (SCK, SD, FS).

ai14136e

t

h(MI)

t

c(SCK)

t

w(SCKH)

t

w(SCKL)

t

su(MI)

NSS input

CPHA=0
CPOL=0

CPHA=0
CPOL=1

MOSI output

MISO input

SCK output

First bit OUT

Last bit OUT

Next bits OUT

First bit IN

Last bit IN

Next bits IN

CPHA=1
CPOL=0

CPHA=1
CPOL=1

SCK output

High

t

v(MO)

t

h(MO)

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Table 149. SAI characteristics

(1)

 

Symbol Parameter 

Conditions Min 

Max 

Unit 

f

MCK

SAI main clock 
output 

-

-

50

MHz

f

SCK

SAI clock 
frequency

(2)

Master transmitter, 2.7 V 

 V

DDIOX

 

 3.6 V

-

26

Master transmitter, 1.71 V 

 V

DDIOX

 

 3.6 V

-

18

Master receiver, 1.71 V 

 V

DDIOX

 

 3.6 V

-

21.5

Slave transmitter, 2.7 V 

 V

DDIOX

 

 3.6 V

-

30

Slave transmitter, 1.71 V 

 V

DDIOX

 

 3.6 V

-

20.5

Slave receiver, 1.71 V 

 V

DDIOX

 

 3.6 V

-

50

t

v(FS)

FS valid time 

Master mode, 2.7 V 

 V

DDIOX

 

 3.6 V

-

16

ns

Master mode 1.71 V 

 V

DDIOX

 

 3.6 V

-

23

t

h(FS)

FS hold time 

Master mode 

7

-

t

su(FS)

FS setup time 

Slave mode 

2.5

-

t

h(FS)

FS hold time 

Slave mode 

1

-

t

su(SD_A_MR)

Data input setup 
time

Master receiver 

4

-

t

su(SD_B_SR)

Slave receiver 

3

-

t

h(SD_A_MR)

Data input hold 
time 

Master receiver 

1

-

t

h(SD_B_SR)

Slave receiver 

1

-

t

v(SD_B_ST)

Data output valid 
time

Slave transmitter (after enable edge),

 

2.7 V 

 V

DDIOX

 

 3.6 V

-

16.5

Slave transmitter (after enable edge),

 

1.71 V 

 V

DDIOX

 

 3.6 V

-

24

t

h(SD_B_ST)

Data output hold 
time

Slave transmitter (after enable edge) 

8

-

t

v(SD_A_MT)

Data output valid 
time

Master transmitter (after enable edge),

 

2.7 V 

 V

DDIOX

 

 3.6 V

-

19

ns

Master transmitter (after enable edge),

 

1.71 V 

 V

DDIOX

 

 3.6 V

-

27.5

t

h(SD_A_MT)

Data output hold 
time 

Master transmitter (after enable edge) 

8

-

1. Evaluated by characterization. Not tested in production.

2. APB clock frequency that must be at least twice SAI clock frequency.

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Figure 79. SAI master timing diagram

Figure 80. SAI slave timing diagram

5.3.41 OTG_FS 

characteristics

          

MS32771V2

SAI_SCK_X
(CKSTR = 1)

SAI_FS_X
(output)

1/fSCK  

SAI_SD_X
(transmit)

tv(FS)

Slot n

SAI_SD_X
(receive)

th(FS)

Slot n+2

tv(SD_MT)

Slot n

tsu(SD_MR)

th(SD_MR)

SAI_SCK_X
(CKSTR = 0)

th(SD_MT)

MS32772V2

SAI_SCK_X
(CKSTR = 1)

SAI_FS_X
(input)

SAI_SD_X
(transmit)

tsu(FS)

Slot n

SAI_SD_X
(receive)

tw(CKH_X)

th(FS)

Slot n+2

tv(SD_ST)

th(SD_ST)

Slot n

tsu(SD_SR)

tw(CKL_X)

th(SD_SR)

1/fSCK

SAI_SCK_X
(CKSTR = 0)

Table 150. OTG_FS characteristics 

Symbol

Parameter

Conditions

Min

Typ

Max Unit

V

DDUSB

USB transceiver operating supply voltage

-

3.0

(1)

-

3.6

V

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DS13737 Rev 10

5.3.42 UCPD 

characteristics

UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 
specifications.

          

5.3.43 JTAG/SWD 

interface characteristics

Unless otherwise specified, the parameters given in the tables below are derived from tests 
performed under the ambient temperature, f

HCLKx

 frequency and V

DD

 supply voltage 

conditions summarized in 

Table 32

, with the following configuration:

Output speed set to OSPEEDRy[1:0] = 10

Capacitive load C

L

 = 30 pF

Measurement points done at 0.5

 × 

V

DD

 level

Refer to 

Section 5.3.15: I/O port characteristics

 for more details on the input/output 

characteristics.

          

R

PUI

Embedded USB_DP pullup value during idle

-

900

-

1575

R

PUR

Embedded USB_DP pullup value during reception

-

1425

-

3090

Z

DRV

Output driver impedance

(2)

High and low driver

28

36

44

1. USB functionality is ensured down to 2.7 V, but some USB electrical characteristics are degraded in 2.7 to 3.0 V range.

2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-). The matching impedance is 

already included in the embedded driver.

Table 150. OTG_FS characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Table 151. UCPD characteristics 

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

DD

UCPD operating supply voltage

Sink mode only

3.0

3.3

3.6

V

Sink and source mode

3.135

3.3

3.465

Table 152. JTAG characteristics

(1)

 

Symbol

Parameter

 Conditions

Min

Typ

Max

Unit

F

TCK

TCK clock frequency

2.7 V 

 V

DD

 

 3.6 V

-

-

38

MHz

1.71 V 

 V

DD

 

 3.6 V

-

-

26

ti

su(TMS)

TMS input setup time

-

1

-

-

ns

ti

h(TMS)

TMS input hold time

-

3

-

-

ti

su(TDI)

TDI input setup time

-

2

-

-

ti

h(TDI)

TDI input hold time

-

1

-

-

t

ov(TDO)

TDO output valid time

2.7 V 

 V

DD

 

 3.6 V

-

9

13

ns

1.71 V 

 V

DD

 

 3.6 V

-

9

19

t

oh(TDO)

TDO output hold time

-

7

-

-

1. Evaluated by characterization. Not tested in production. 

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Figure 81. JTAG timing diagram

Figure 82. SWD timing diagram

Table 153. SWD characteristics

(1)

 

Symbol

Parameter

 Conditions

Min

Typ

Max

Unit

F

SWCLK

SWCLK clock frequency

2.7 V 

 V

DD

 

 3.6 V

-

-

66.5

MHz

1.71 V 

 V

DD

 

 3.6 V

-

-

43

ti

su(SWDIO)

SWDIO input setup time

-

1

-

-

ns

ti

h(SWDIO)

SWDIO input hold time

-

2.5

-

-

t

ov(SWDIO)

SWDIO output valid time

2.7 V 

 V

DD

 

 3.6 V

-

10.5

15

1.71 V 

 V

DD

 

 3.6 V

-

10.5

23

t

oh(SWDIO)

SWDIO output hold time

-

7.5

-

-

1. Evaluated by characterization. Not tested in production. 

MSv40458V1

TDI/TMS

TCK

TDO

t

c(TCK)

t

w(TCKL)

t

w(TCKH)

t

h(TMS/TDI)

t

su(TMS/TDI)

t

ov(TDO)

t

oh(TDO)

MSv40459V1

SWDIO

SWCLK

SWDIO  

t

c(SWCLK)

t

wSWCLKL)

t

w(SWCLKH)

t

h(SWDIO)

t

su(SWDIO)

t

ov(SWDIO)

t

oh(SWDIO)

(receive)

(transmit)

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DS13737 Rev 10

6 Package 

information

In order to meet environmental requirements, ST offers these devices in different grades of 
ECOPACK packages, depending on their level of environmental compliance. ECOPACK 
specifications, grade definitions and product status are available at: 

www.st.com

ECOPACK is an ST trademark.

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Package information

337

6.1 UFQFPN48 

package information (A0B9)

This UFQFPN is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 83. UFQFPN48 – Outline

1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN48 package. It is recommended to connect 

and solder this back-side pad to PCB ground.

D1

E1

EXPOSED PAD

E2

e

D2

PIN 1 idenfier

BOTTOM VIEW

L

A

A3

C

FRONT VIEW

DETAIL A

SEATING PLANE

LEADS COPLANARITY

C

ddd

SEATING PLANE

A1

A1

A

C

C

ddd

PIN 1 IDENTIFIER

LASER MAKER AREA

E

D

TOP VIEW

A0B9_UFQFPN48_ME_V4

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DS13737 Rev 10

          

Figure 84. UFQFPN48 – Footprint example

1. Dimensions are expressed in millimeters.

Table 154. UFQFPN48 – Mechanical data 

Symbol

millimeters

inches

(1)

1. Values in inches are converted from mm and rounded to four decimal digits.

Min

Typ

Max

Min

Typ

Max

A

0.500

0.550

0.600

0.0197

0.0217

0.0236

A1

0.000

0.020

0.050

0.0000

 0.0008

0.0020

A3

-

0.152

-

-

0.0060

-

b

0.200

0.250

0.300

0.0079

0.0098

0.0118

D

(2)

2. Dimensions D and E do not include mold protrusion, not exceed 0.15 mm.

6.900

7.000

7.100

0.2717

0.2756

0.2795

D1

5.400

5.500

5.600

0.2126

0.2165

0.2205

D2

(3)

3. Dimensions D2 and E2 are not in accordance with JEDEC.

5.500

5.600

5.700

0.2165

0.2205

0.2244

E

(2)

6.900

7.000

7.100

0.2717

0.2756

0.2795

E1

5.400

5.500

5.600

0.2126

0.2165

0.2205

E2

(3)

5.500

5.600

5.700

0.2165

0.2205

0.2244

e

-

0.500

-

-

0.0197

-

L

0.300

0.400

0.500

0.0118

0.0157

0.0197

ddd

-

-

0.080

-

-

0.0031

7.30

7.30

0.20

0.30

0.55

0.50

5.80

6.20

6.20

5.60

5.60

5.80

0.75

A0B9_UFQFPN48_FP_V3

48

1

12

13

24

25

36

37

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STM32U575xx

Package information

337

Device marking for UFQFPN48

The following figure gives an example of topside marking versus pin 1 position identifier 
location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which depend on supply chain operations, are 
not indicated below.

Figure 85. UFQFPN48 marking example (package top view) 

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet 

qualified and therefore not approved for use in production. ST is not responsible for any consequences 

resulting from such use. In no event will ST be liable for the customer using any of these engineering 

samples in production. ST’s Quality department must be contacted prior to any decision to use these 

engineering samples to run a qualification activity.

MSv67876V1

Date code

Pin 1 identifier

CIU6

Product identification

(1)

R

Y WW

STM32U575

Revision code

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DS13737 Rev 10

6.2 

LQFP48 package information (5B)

This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package.

Note:

See list of notes in the notes section.

Figure 86. LQFP48 - Outline

(15)

SECTION A-A

GAUGE PLANE

B

B SECTION B-B

H

L

S

R1

R2

SECTION B-B

b

b1

c

c1

WITH PLATING

BASE METAL

1

3

2

5B_LQFP48_ME_V1

(6)

aaa C A-B D

4x N/4 TIPS

bbb H A-B D 4x

ddd

C A-B D

(12)

(13)

(N – 4)x e

ccc C

A

D 1/4

E 1/4

0.05

A1

A2

b

C

(3)

E1

D 1/4

(3)

(4)

A

1
2
3

(2) (5)

D1

D

D (3)

(4)

E

(Section A-A)

B

E 1/4

N

(10)

(5)

(2)

(6)

A

A

BOTTOM VIEW

TOP VIEW

(L1)

(2)

0.25

(11)

(9) (11)

(11)

(11)

(11)

(1)

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Package information

337

          

Table 155. LQFP48 - Mechanical data 

Symbol

millimeters

inches

(14)

Min

Typ

Max

Min

Typ

Max

A

 -

 -

1.60

 -

 -

0.0630

A1

(12)

0.05

 -

0.15

0.0020

0.0059

A2

1.35

1.40

1.45

0.0531

0.0551

0.0571

b

(9)(11)

0.17

0.22

0.27

0.0067

0.0087

0.0106

b1

(11)

0.17

0.20

0.23

0.0067

0.0079

0.0090

c

(11)

0.09

 -

0.20

0.0035

0.0079

c1

(11)

0.09

 -

0.16

0.0035

0.0063

D

(4)

9.00 BSC

0.3543 BSC

D1

(2)(5)

7.00 BSC

0.2756 BSC

E

(4)

9.00 BSC

0.3543 BSC

E1

(2)(5)

7.00 BSC

0.2756 BSC

e

0.50 BSC

0.1970 BSC

L

0.45

0.60

0.75

0.0177

0.0236

0.0295

L1

 1.00 REF

 0.0394 REF

N

(13)

48

θ

3.5°

3.5°

θ1

-

-

-

-

θ2

10°

12°

14°

10°

12°

14°

θ3

10°

12°

14°

10°

12°

14°

R1

0.08

-

-

0.0031

-

-

R2

0.08

-

0.20

0.0031

-

0.0079

S

0.20

-

-

0.0079

-

-

aaa

(1)(7)

0.20

0.0079

bbb

(1)(7)

0.20

0.0079

ccc

(1)(7)

0.08

0.0031

ddd

(1)(7)

0.08

0.0031

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DS13737 Rev 10

Notes:

1.

Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

2.  The Top package body size may be smaller than the bottom package size by as much 

as 0.15 mm.

3.  Datums A-B and D to be determined at datum plane H.
4.  To be determined at seating datum plane C.
5.  Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash 

or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size 
dimensions including mold mismatch.

6.  Details of pin 1 identifier are optional but must be located within the zone indicated.
7.  All Dimensions are in millimeters.
8.  No intrusion allowed inwards the leads.
9.  Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall 

not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. 
Dambar cannot be located on the lower radius or the foot. Minimum space between 
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

10.  Exact shape of each corner is optional.
11.  These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm 

from the lead tip.

12.  A1 is defined as the distance from the seating plane to the lowest point on the package 

body.

13.  “N” is the number of terminal positions for the specified body size.
14.  Values in inches are converted from mm and rounded to 4 decimal digits.
15.  Drawing is not to scale.

Figure 87. LQFP48 - Footprint example

1. Dimensions are expressed in millimeters.

12

24

1

37

36

5.80

0.30

25

1.20

0.50

13

48

9.70 7.30

9.70

0.20

5B_LQFP48_FP_V1

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Package information

337

Device marking for LQFP48

The following figure gives an example of topside marking versus pin 1 position identifier 
location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which depend on supply chain operations, are 
not indicated below.

Figure 88. LQFP48 marking example (package top view) 

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet 

qualified and therefore not approved for use in production. ST is not responsible for any consequences 

resulting from such use. In no event will ST be liable for the customer using any of these engineering 

samples in production. ST’s Quality department must be contacted prior to any decision to use these 

engineering samples to run a qualification activity.

MSv67876V1

Date code

Pin 1 identifier

CIU6

Product identification

(1)

R

Y WW

STM32U575

Revision code

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Package information

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DS13737 Rev 10

6.3 

LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.

Note:

See list of notes in the notes section.

Figure 89. LQFP64 - Outline

(15)

D 1/4

E 1/4

(6)

aaa C A-B D

4x N/4 TIPS

bbb H A-B D 4x

(13) (N – 4)x e

0.05

A

A2 A1

(12)

b

ddd

C A-B D

ccc

C

C

D

(5) (2)

(4)

D1

D (3)

D 1/4

E 1/4

(6)

1
2
3

(3) A

B (3)

(5)
(2)

E1

E

A

A

(Section A-A)

(4)

5W_LQFP64_ME_V1

(10)

N

BOTTOM VIEW

TOP VIEW

SECTION A-A

GAUGE PLANE

B

B SECTION B-B

H

L

S

R1

R2

SECTION B-B

b

b1

c

c1

WITH PLATING

BASE METAL

1

3

2

(L1)

(2)

0.25

(11)

(9) (11)

(11)

(11)

(11)

(1)

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Table 156. LQFP64 - Mechanical data 

Symbol

millimeters

inches

(14)

Min

Typ

Max

Min

Typ

Max

A

-

-

1.60

-

-

0.0630

A1

(12)

0.05

-

0.15

0.0020

-

0.0059

A2

1.35

1.40

1.45

0.0531

0.0551

0.0570

b

(9)(11)

0.17

0.22

0.27

0.0067

0.0087

0.0106

b1

(11)

0.17

0.20

0.23

0.0067

0.0079

0.0091

c

(11)

0.09

-

0.20

0.0035

-

0.0079

c1

(11)

0.09

-

0.16

0.0035

-

0.0063

D

(4)

12.00 BSC

0.4724 BSC

D1

(2)(5)

10.00 BSC

0.3937 BSC

E

(4)

12.00 BSC

0.4724 BSC

E1

(2)(5)

10.00 BSC

0.3937 BSC

e

0.50 BSC

0.1970 BSC

L

0.45

0.60

0.75

0.0177

0.0236

0.0295

L1

1.00 REF

0.0394 REF

N

(13)

64

θ

3.5°

3.5°

θ1

-

-

-

-

θ2

10°

12°

14°

10°

12°

14°

θ3

10°

12°

14°

10°

12°

14°

R1

0.08

-

-

0.0031

-

-

R2

0.08

-

0.20

0.0031

-

0.0079

S

0.20

-

-

0.0079

-

-

aaa

(1)

0.20

0.0079

bbb

(1)

0.20

0.0079

ccc

(1)

0.08

0.0031

ddd

(1)

0.08

0.0031

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DS13737 Rev 10

Notes:

1.

Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

2.  The Top package body size may be smaller than the bottom package size by as much 

as 0.15 mm.

3.  Datums A-B and D to be determined at datum plane H.
4.  To be determined at seating datum plane C.
5.  Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash 

or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size 
dimensions including mold mismatch.

6.  Details of pin 1 identifier are optional but must be located within the zone indicated.
7.  All Dimensions are in millimeters.
8.  No intrusion allowed inwards the leads.
9.  Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall 

not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. 
Dambar cannot be located on the lower radius or the foot. Minimum space between 
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

10.  Exact shape of each corner is optional.
11.  These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm 

from the lead tip.

12.  A1 is defined as the distance from the seating plane to the lowest point on the package 

body.

13.  “N” is the number of terminal positions for the specified body size.
14.  Values in inches are converted from mm and rounded to 4 decimal digits.
15.  Drawing is not to scale.

Figure 90. LQFP64 - Footprint example

1. Dimensions are expressed in millimeters.

48

32

49

64

17

1

16

1.20

0.30

33

10.30

12.70

10.30

0.5

7.80

12.70

5W_LQFP64_FP_V2

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Device marking for LQFP64

The following figure gives an example of topside marking orientation versus pin 1 identifier 
location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which also depend on supply chain operations, 
are not indicated below.

Figure 91. LQFP64 marking example (package top view) 

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified 

and therefore not approved for use in production. ST is not responsible for any consequences resulting 

from such use. In no event will ST be liable for the customer using any of these engineering samples in 

production. ST’s Quality department must be contacted prior to any decision to use these engineering 

samples to run a qualification activity. 

MSv67878V1

Date code

Pin 1 identifier

RIT6

Product identification

(1)

Revision code

R

Y WW

STM32U575

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DS13737 Rev 10

6.4 

WLCSP90 package information (B01C)

WLCSP is a 90 balls, 4.20 x 3.95 mm, 0.4 mm pitch, wafer level chip scale package. 

Figure 92. WLCSP90 - Outline

1. Drawing is not to scale.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.

Table 157. WLCSP90 - Mechanical data 

Symbol

millimeters

inches

(1)

Min

Typ

Max

Min

Typ

Max

A

(2)

-

-

0.59

-

-

0.023

A1

-

0.18

-

-

0.007

-

A2

-

0.38

-

-

0.015

-

A3

(3)

-

0.025

-

-

0.001

-

b

0.22

0.25

0.28

0.009

0.010

0.011

D

4.19

4.20

4.21

0.165

0.165

0.166

E

3.93

3.95

3.97

0.155

0.156

0.156

e

-

0.40

-

-

0.016

-

Z

B01C_WLCSP90_ME_V2

Z

BOTTOM VIEW

TOP VIEW

SIDE VIEW

FRONT VIEW

DETAIL A

ROTATED 90

SEATING PLANE

D

e

e

e2 E

F

G

e1

A1 BALL LOCATION

A1

B2

B4

aaa

(4x)

bbb Z

A1

A2

A

A3

A2

b

BUMP

eee

A1

b (90x)

ccc
ddd

Z X Y

Z

DETAIL A

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Figure 93. WLCSP90 - Recommended footprint

          

e1

-

3.40

-

-

0.134

-

e2

-

3.12

-

-

0.123

-

F

(4)

-

0.400

-

-

0.016

-

G

(4)

-

0.416

-

-

0.016

-

aaa

-

-

0.10

-

-

0.004

bbb

-

-

0.10

-

-

0.004

ccc

-

-

0.10

-

-

0.004

ddd

-

-

0.05

-

-

0.002

eee

-

-

0.05

-

-

0.002

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal 

and tolerances values of A1 and A2.

3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process 

capability.

4. Calculated dimensions are rounded to the 3rd decimal place

Table 158. WLCSP90 - Recommended PCB design rules

Dimension

Recommended values

Pitch

0.4 mm

Dpad

0,225 mm

Dsm

0.290 mm typ. (depends on soldermask registration tolerance)

Stencil opening

0.250 mm

Stencil thickness

0.100 mm

Table 157. WLCSP90 - Mechanical data (continued)

Symbol

millimeters

inches

(1)

Min

Typ

Max

Min

Typ

Max

B03P_WLCSP36_DIE464_FP_V1

Dpad

Dsm

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DS13737 Rev 10

Device marking for WLCSP90

The following figure gives an example of topside marking orientation versus pin 1 identifier 
location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which also depend on supply chain operations, 
are not indicated below.

Figure 94. WLCSP90 marking example (package top view) 

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified 

and therefore not approved for use in production. ST is not responsible for any consequences resulting 

from such use. In no event will ST be liable for the customer using any of these engineering samples in 

production. ST’s Quality department must be contacted prior to any decision to use these engineering 

samples to run a qualification activity. 

MSv67879V1

Pin 1 identifier

Product identification

(1)

R

Y WW

U575OI6Q

Revision code

Date code

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DS13737 Rev 10

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Package information

337

6.5 LQFP100 

package information (1L)

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.

Note:

See list of notes in the notes section.

Figure 95. LQFP100 - Outline

(15)

D1/4

E1/4

4x N/4 TIPS

aaa C A-B D

bbb H A-B D

4x

(N-4) x e

A

0.05

A2 A1

b

aaa

C A-BD

ccc C

C

D

D1

D

N

A

1
2
3

SECTION A-A

A

A

B

E

E1

SECTION A-A

GAUGE PLANE

B

B SECTION B-B

H

E1/4

D1/4

L

S

R1

R2

SECTION B-B

b

b1

c

c1

WITH PLATING

BASE METAL

TOP VIEW

SIDE VIEW

BOTTOM VIEW

1L_LQFP100_ME_V3

(6)

(6)

(10)

ș

2

ș

ș

ș

(13)

(12)

(5)

(2)

(4)

(4)

(5)

(2)

(3)

(L1)

(9) (11)

(11)

(11)

(11)

(2)

(11)

(1)

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DS13737 Rev 10

          

Table 159. LQFP100 - Mechanical data 

Symbol

millimeters

inches

(14)

Min

Typ

Max

Min

Typ

Max

A

-

1.50

1.60

-

0.0590

0.0630

A1

(12)

0.05

-

0.15

0.0019

-

0.0059

A2

1.35

1.40

1.45

0.0531

0.0551

0.0570

b

(9)(11)

0.17

0.22

0.27

0.0067

0.0087

0.0106

b1

(11)

0.17

0.20

0.23

0.0067

0.0079

0.0090

c

(11)

0.09

-

0.20

0.0035

-

0.0079

c1

(11)

0.09

-

0.16

0.0035

-

0.0063

D

(4)

16.00 BSC

0.6299 BSC

D1

(2)(5)

14.00 BSC

0.5512 BSC

E

(4)

16.00 BSC

0.6299 BSC

E1

(2)(5)

14.00 BSC

0.5512 BSC

e

0.50 BSC

0.0197 BSC

L

0.45

0.60

0.75

0.177

0.0236

0.0295

L1

(1)(11)

1.00

-

0.0394

-

N

(13)

100

θ

3.5°

3.5°

θ1

-

-

-

-

θ2

10°

12°

14°

10°

12°

14°

θ3

10°

12°

14°

10°

12°

14°

R1

0.08

-

-

0.0031

-

-

R2

0.08

-

0.20

0.0031

-

0.0079

S

0.20

-

-

0.0079

-

-

aaa

(1)

0.20

0.0079

bbb

(1)

0.20

0.0079

ccc

(1)

0.08

0.0031

ddd

(1)

0.08

0.0031

STM32U575RGT6-html.html

DS13737 Rev 10

323/346

STM32U575xx

Package information

337

Notes:

1.

Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

2.  The Top package body size may be smaller than the bottom package size by as much 

as 0.15 mm.

3.  Datums A-B and D to be determined at datum plane H.
4.  To be determined at seating datum plane C.
5.  Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash 

or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size 
dimensions including mold mismatch.

6.  Details of pin 1 identifier are optional but must be located within the zone indicated.
7.  All Dimensions are in millimeters.
8.  No intrusion allowed inwards the leads.
9.  Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall 

not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. 
Dambar cannot be located on the lower radius or the foot. Minimum space between 
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

10.  Exact shape of each corner is optional.
11.  These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm 

from the lead tip.

12.  A1 is defined as the distance from the seating plane to the lowest point on the package 

body.

13.  “N” is the number of terminal positions for the specified body size.
14.  Values in inches are converted from mm and rounded to 4 decimal digits.
15.  Drawing is not to scale.

Figure 96. LQFP100 - Footprint example

1. Dimensions are expressed in millimeters.

75

51

50

76

0.5

0.3

16.7

14.3

100

26

12.3

25

1.2

16.7

1

1L_LQFP100_FP_V1

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DS13737 Rev 10

Device marking for LQFP100

The following figure gives an example of topside marking orientation versus pin 1 identifier 
location. The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which also depend on supply chain operations, 
are not indicated below.

Figure 97. LQFP100 marking example (package top view) 

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified 

and therefore not approved for use in production. ST is not responsible for any consequences resulting 

from such use. In no event will ST be liable for the customer using any of these engineering samples in 

production. ST’s Quality department must be contacted prior to any decision to use these engineering 

samples to run a qualification activity. 

MSv67880V1

Revision code

Date code

Pin 1 identifier

575VIT6

Product identification

(1)

STM32U

R

Y WW

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DS13737 Rev 10

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Package information

337

6.6 UFBGA132 

package information (A0G8)

This UFBGA is a 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package.

Figure 98. UFBGA132 - Outline

1. Drawing is not to scale.

          

Table 160. UFBGA132 - Mechanical data 

Symbol

millimeters

inches

(1)

Min

Typ

Max

Min

Typ

Max

A

-

-

0.600

-

-

0.0236

A1

-

-

0.110

-

-

0.0043

A2 -

0.450

-

-

0.0177

-

A3 -

0.130

-

-

0.0051

-

A4 -

0.320

-

-

0.0126 

-

b

0.240

0.290

0.340

0.0094

0.0114

0.0134

D

6.850

7.000

7.150

0.2697

0.2756

0.2815

D1

-

5.500

-

-

0.2165

-

E

6.850

7.000

7.150

0.2697

0.2756

0.2815

E1

-

5.500

-

-

0.2165

-

UFBGA132_A0G8_ME_V2

SEATING 
PLANE

A4

A1

e

Z

Z

D

A

eee

C A B

fff

Øb (132 balls)

Ø
Ø

M

M
M

E

TOP VIEW

BOTTOM VIEW

12

1

e

A

A2

C

A

B

A1 ball identifier

b

D1

E1

ddd C

A3

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DS13737 Rev 10

Figure 99. UFBGA132 - Footprint example

          

e

-

0.500

-

-

0.0197

-

Z

-

0.750

-

-

0.0295

-

ddd

-

0.080

-

-

0.0031

-

eee

-

0.150

-

-

0.0059

-

fff

-

0.050

-

-

0.0020

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 161. UFBGA132 - Example of PCB design rules (0.5 mm pitch BGA) 

Dimension

Values

Pitch

0.5 mm

Dpad

0.280 mm

Dsm

0.370 mm typ. (depends on the soldermask 
registration tolerance)

Stencil opening

0.280 mm

Stencil thickness

Between 0.100 mm and 0.125 mm

Pad trace width

0.100 mm

Ball diameter

0.280 mm

Table 160. UFBGA132 - Mechanical data (continued)

Symbol

millimeters

inches

(1)

Min

Typ

Max

Min

Typ

Max

BGA_WLCSP_FT_V1

Dsm

Dpad

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327/346

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Package information

337

Device marking for UFBGA132

The following figure gives an example of topside marking orientation versus pin 1 identifier 
location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which also depend on supply chain operations, 
are not indicated below.

Figure 100. UFBGA132 marking example (package top view) 

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified 

and therefore not approved for use in production. ST is not responsible for any consequences resulting 

from such use. In no event will ST be liable for the customer using any of these engineering samples in 

production. ST’s Quality department must be contacted prior to any decision to use these engineering 

samples to run a qualification activity. 

MSv67881V1

Date code

575QII6

Product identification

(1)

Y WW

STM32U

Revision code

R

Pin 1 identifier

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DS13737 Rev 10

6.7 LQFP144 

package information (1A)

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.

Note:

See list of notes in the notes section.

Figure 101. LQFP144 - Outline

(15)

SECTION A-A

GAUGE PLANE

B

B SECTION B-B

H

L

(L1)

S

R1

R2

SECTION B-B

b

b1

c

c1

WITH PLATING

BASE METAL

1

3

2

(6)

D 1/4

E 1/4

BOTTOM VIEW

ddd

C A-B D

0.05

(12)

A1

A2

A

aaa C A-B D

(N-4)x e

1A_LQFP144_ME_V2

4x

H A-B D

bbb

b

C

ccc C

D 1/4

E 1/4

D

D1

(3)

N

1

(10)

2

3

(6)

(3) A

(3)

B

(2)
(5)

E1

E

(2) (5)

(4)

(4)

A

A

(Section A-A)

D

TOP VIEW

(2)

0.25

(11)

4x N/4 TIPS

(9) (11)

(11)

(11)

(11)

(1)

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Table 162. LQFP144 - Mechanical data 

Symbol

millimeters

inches

(14)

Min

Typ

Max

Min

Typ

Max

A

-

-

1.60

-

-

0.0630

A1

(12)

0.05

-

0.15

0.0020

-

0.0059

A2

1.35

1.40

1.45

0.0531

0.0551

0.0571

b

(9)(11)

0.17

0.22

0.27

0.0067

0.0087

0.0106

b1

(11)

0.17

0.20

0.23

0.0067

0.0079

0.0090

c

(11)

0.09

-

0.20

0.0035

-

0.0079

c1

(11)

0.09

-

0.16

0.0035

-

0.0063

D

(4)

22.00 BSC

0.8661 BSC

D1

(2)(5)

20.00 BSC

0.7874 BSC

E

(4)

22.00 BSC

0.8661 BSC

E1

(2)(5)

20.00 BSC

0.7874 BSC

e

0.50 BSC

0.0197 BSC

L

0.45

0.60

0.75

0.0177

0.0236

0.0295

L1

1.00 REF

0.0394 REF

N

(13)

144

θ

3.5°

3.5°

θ1

-

-

-

-

θ2

10°

12°

14°

10°

12°

14°

θ3

10°

12°

14°

10°

12°

14°

R1

0.08

-

-

0.0031

-

-

R2

0.08

-

0.20

0.0031

-

0.0079

S

0.20

-

-

0.0079

-

-

aaa

0.20

0.0079

bbb

0.20

0.0079

ccc

0.08

0.0031

ddd

0.08

0.0031

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DS13737 Rev 10

Notes:

1.

Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

2.  The Top package body size may be smaller than the bottom package size by as much 

as 0.15 mm.

3.  Datums A-B and D to be determined at datum plane H.
4.  To be determined at seating datum plane C.
5.  Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash 

or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size 
dimensions including mold mismatch.

6.  Details of pin 1 identifier are optional but must be located within the zone indicated.
7.  All Dimensions are in millimeters.
8.  No intrusion allowed inwards the leads.
9.  Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall 

not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. 
Dambar cannot be located on the lower radius or the foot. Minimum space between 
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

10.  Exact shape of each corner is optional.
11.  These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm 

from the lead tip.

12.  A1 is defined as the distance from the seating plane to the lowest point on the package 

body.

13.  “N” is the number of terminal positions for the specified body size.
14.  Values in inches are converted from mm and rounded to 4 decimal digits.
15.  Drawing is not to scale.

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Figure 102. LQFP144 - Footprint example

1. Dimensions are expressed in millimeters.

0.50

0.35

19.90

17.85

22.60

1.35

22.60

19.90

1

36

37

72

73

108

109

144

1A_LQFP144_FP

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DS13737 Rev 10

Device marking for LQFP144

The following figure gives an example of topside marking orientation versus pin 1 identifier 
location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which also depend on supply chain operations, 
are not indicated below.

Figure 103. LQFP144 marking example (package top view) 

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified 

and therefore not approved for use in production. ST is not responsible for any consequences resulting 

from such use. In no event will ST be liable for the customer using any of these engineering samples in 

production. ST’s Quality department must be contacted prior to any decision to use these engineering 

samples to run a qualification activity. 

MSv67882V1

Revision code

Date code

Product identification

(1)

STM32U575ZIT6

R

Y WW

Pin 1 identifier

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Package information

337

6.8 UFBGA169 

package information (A0YV)

This UFBGA is a 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.

Figure 104. UFBGA169 - Outline

1. Drawing is not to scale.

          

Table 163. UFBGA169 - Mechanical data 

Symbol

millimeters

inches

(1)

Min.

Typ.

Max.

Min.

Typ.

Max.

A 0.460 

0.530 

0.600 

0.0181 0.0209 0.0236 

A1 0.050 0.080 0.110  0.0020 0.0031 0.0043 

A2 0.400 0.450 0.500  0.0157 0.0177 0.0197 

A3 -

0.130 -

-

0.0051 

-

A4 0.270 0.320 0.370  0.0106 0.0126 0.0146 

b 0.230 

0.280 

0.330 

0.0091

0.0110 

0.0130

D 6.950 

7.000 

7.050 

0.2736 0.2756 0.2776 

D1 5.950 6.000 6.050 

0.2343

0.2362

0.2382

E 6.950 

7.000 

7.050 

0.2736 0.2756 0.2776 

E1 5.950 6.000 6.050 

0.2343

0.2362

0.2382

A0YV_ME_V2

Seating plane

A2

A1

A

e

F

F

e

N

A

BOTTOM VIEW

E

D

TOP VIEW

Øb (169 balls) 

 

Y

X

Y

eee

Ø

M

fff

Ø

M

Z
Z

X

A1 ball 

identifier

A1 ball 

index area

b

D1

E1

A4

A3

13

1

Z

Z

ddd

SIDE VIEW

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DS13737 Rev 10

Figure 105. UFBGA169 - Footprint example

          

Note:

Non-solder mask defined (NSMD) pads are recommended.

Note:

4 to 6 mils solder paste screen printing process.

e  

-

0.500 

-  - 

0.0197 

F 0.450 

0.500 

0.550 

0.0177

0.0197 0.0217

ddd 

-

-

 0.100 

-

-

 0.0039

eee -

-

0.150

-

-

0.0059 

fff -

-

0.050

-

-

0.0020 

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 164. UFBGA169 - Example of PCB design rules (0.5 mm pitch BGA) 

Dimension

Values

Pitch

0.5 mm

Dpad

0.27 mm

Dsm

0.35 mm typ. (depends on the soldermask 
registration tolerance)

Solder paste

0.27 mm aperture diameter.

Table 163. UFBGA169 - Mechanical data (continued)

Symbol

millimeters

inches

(1)

Min.

Typ.

Max.

Min.

Typ.

Max.

BGA_WLCSP_FT_V1

Dsm

Dpad

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Package information

337

Device marking for UFBGA169

The following figure gives an example of topside marking orientation versus pin 1 identifier 
location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which also depend on supply chain operations, 
are not indicated below.

Figure 106. UFBGA169 marking example (package top view) 

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified 

and therefore not approved for use in production. ST is not responsible for any consequences resulting 

from such use. In no event will ST be liable for the customer using any of these engineering samples in 

production. ST’s Quality department must be contacted prior to any decision to use these engineering 

samples to run a qualification activity. 

MSv67883V1

Date code

575AII6

Product identification

(1)

Y WW

STM32U

Revision code

R

Pin 1 identifier

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DS13737 Rev 10

6.9 Package 

thermal characteristics

The maximum chip-junction temperature, T

J

 max, in degrees Celsius, can be calculated 

using the following equation:

T

J

 max = T

A

 max + (P

D

 max

 × 

 

Θ

JA

)

where:

T

A

 max is the maximum ambient temperature in °C.

Θ

JA 

is the package junction-to-ambient thermal resistance in °C/W.

P

D

 max is the sum of P

INT

 max and P

I/O

 max (P

D

 max = P

INT

 max + P

I/O

 max).

P

INT

 max is the product of I

DD

 and V

DD

, expressed in Watts. This is the maximum chip 

internal power.

P

I/O

 max represents the maximum power dissipation on output pins:

P

I/O

 max = 

(V

OL

 × 

I

OL

) + 

((V

DDIOx

 - V

OH

)

 × 

I

OH

)

taking into account the actual V

OL

/I

OL

 and V

OH

/I

OH

 of the I/Os at low and high level in the 

application.

          

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6.9.1 Reference 

documents

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural 
Convection (Still Air) available on www.jedec.org.

For information on thermal management, refer to application note “Guidelines for 
thermal management on STM32 applications” (AN5036) available on www.st.com.

Table 165. Package thermal characteristics 

Symbol

Parameter

Package

Value

Unit

Θ

JA

Thermal resistance junction-ambient

LQFP48 7 x 7 mm

45.8

°C/W

UFQFPN48 7 x 7 mm

26.9

LQFP64 10 x 10 mm

39.6

WLCSP90 4.2 x 3.95 mm

42.3

LQFP100 - 14 × 14 m

34.4

UFBGA132 7 x 7 mm

35.2

LQFP144 20 x 20 mm

35.9

UFBGA169 7 x 7 mm

33.7

Θ

JB

Thermal resistance junction-board

LQFP48 7 x 7 mm

23.4

UFQFPN48 7 x 7 mm

11.2

LQFP64 10 x 10 mm

22

WLCSP90 4.2 x 3.95 mm

27.5

LQFP100 - 14 × 14 m

20.3

UFBGA132 7 x 7 mm

20.7

LQFP144 20 x 20 mm

24.8

UFBGA169 7 x 7 mm

19.3

Θ

JC

Thermal resistance junction-top case

LQFP48 7 x 7 mm

10.7

UFQFPN48 7 x 7 mm

8

LQFP64 10 x 10 mm

9.0

WLCSP90 4.2 x 3.95 mm

1.6

LQFP100 - 14 × 14 m

7.4

UFBGA132 7 x 7 mm

8.3

LQFP144 20 x 20 mm

7.6

UFBGA169 7 x 7 mm

8.3

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DS13737 Rev 10

7 Ordering 

information 

For a list of available options (such as speed or package) or for further information on any 
aspect of this device, contact the nearest ST sales office.

Example:

STM32

U       575     V

I     T     6   Q  TR

Device family

STM32 = Arm

 

based 32-bit microcontroller

Product type

U = ultra-low-power

Device subfamily

575 = STM32U575xx with OTG

Pin count

C = 48 pins
R = 64 pins
O = 90 pins
V = 100 pins
Q = 132 balls
Z = 144 pins
A = 169 balls

Flash memory size

G = 1 Mbyte
I = 2 Mbytes

Package

T = LQFP 
I = UFBGA (7 x 7 mm) 
U = UFQFPN 
Y = WLCSP

Temperature range

6 = Industrial temperature range, –40 to 85 °C (105 °C junction)

3 = Industrial temperature range, –40 to 125 °C (130 °C junction)

Dedicated pinout

Q = Dedicated pinout supporting SMPS step-down converter

Packing

TR = tape and reel

xxx = programmed parts

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Important security notice

339

Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, 
which is why the ST product(s) identified in this documentation may be certified by various 
security certification bodies and/or may implement our own security measures as set forth 
herein. However, no level of security certification and/or built-in security measures can 
guarantee that ST products are resistant to all forms of attacks. As such, it is the 
responsibility of each of ST's customers to determine if the level of security provided in an 
ST product meets the customer needs both in relation to the ST product alone, as well as 
when combined with other components and/or software for the customer end product or 
application. In particular, take note that:

ST products may have been certified by one or more security certification bodies, such 
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation 
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST 
product(s) referenced herein have received security certification along with the level 
and current status of such certification, either visit the relevant certification standards 
website or go to the relevant product page on www.st.com for the most up to date 
information. As the status and/or level of security certification for an ST product can 
change from time to time, customers should re-check security certification status/level 
as needed. If an ST product is not shown to be certified under a particular security 
standard, customers should not assume it is certified. 

Certification bodies have the right to evaluate, grant and revoke security certification in 
relation to ST products. These certification bodies are therefore independently 
responsible for granting or revoking security certification for an ST product, and ST 
does not take any responsibility for mistakes, evaluations, assessments, testing, or 
other activity carried out by the certification body with respect to any ST product. 

Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open 
standard technologies which may be used in conjunction with an ST product are based 
on standards which were not developed by ST. ST does not take responsibility for any 
flaws in such cryptographic algorithms or open technologies or for any methods which 
have been or may be developed to bypass, decrypt or crack such algorithms or 
technologies. 

While robust security testing may be done, no level of certification can absolutely 
guarantee protections against all attacks, including, for example, against advanced 
attacks which have not been tested for, against new or unidentified forms of attack, or 
against any form of attack when using an ST product outside of its specification or 
intended use, or in conjunction with other components or software which are used by 
customer to create their end product or application. ST is not responsible for resistance 
against such attacks. As such, regardless of the incorporated security features and/or 
any information or support that may be provided by ST, each customer is solely 
responsible for determining if the level of attacks tested for meets their needs, both in 
relation to the ST product alone and when incorporated into a customer end product or 
application. 

All security features of ST products (inclusive of any hardware, software, 
documentation, and the like), including but not limited to any enhanced security 
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT 
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS 
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF 
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the 
applicable written and signed contract terms specifically provide otherwise.

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DS13737 Rev 10

9 Revision 

history 

          

Table 166. Document revision history 

Date

Revision

Changes

02-Sep-2021

1

Initial release

24-Sep-2021

2

Updated:

Figure 24

 and 

Figure 25: STM32U575xQ power supply scheme (with SMPS)

 

– Figure 28: AC timing diagram for high-speed external clock source
– Figure 29: AC timing diagram for low-speed external square clock source

– V

DDCoeff

 values in 

Table 35: Embedded internal voltage reference

– I

DD(RUN) 

Range 2 values in 

Table 36

 and 

Table 37

– New consumption 

Table 39

Table 41

Table 44

Table 45

Table 49

Table 51

Table 53

Table 55

Table 57

Table 59

Table 65

– All values in consumption 

Table 52

Table 54

Table 56

Table 58

Table 64

– All values in 

Table 70

Table 71

Table 72

– USER TROM COVERAGE removed in 

Table 79: MSI oscillator characteristics

Table 82: PLL characteristics

19-Nov-2021

3

Updated:
– ‘legacy’ replaced by ‘without SMPS’ in 

Table 2: STM32U575xx features and 

peripheral counts

– PSSI in 

Table 10: Functionalities depending on the working mode

Table 37

 and new 

Table 38: Current consumption in Run mode on SMPS, code with 

data processing running from Flash memory, ICACHE ON (1-way), prefetch ON, 
V

DD

 = 3.0 V

Table 44

 and new 

Table 45: Current consumption in Sleep mode on SMPS, Flash 

memory in power down, V

DD

 = 3.0 V

– Table 46: SRAM1/SRAM3 current consumption in Run/Sleep mode with LDO and 

SMPS

– t

wu(Sleep)

 max in 

Table 73: Low-power mode wakeup timings on SMPS

– Footnote 8 on 

Table 81: MSI oscillator characteristics

– t

SU(RX)

 in 

Table 145: USART characteristics

Section 6.5: LQFP100 package information

13-Dec-2021

4

Updated:
– FMC_A16 and FMC_A17 in 

Table 26: STM32U575xx pin definitions

 and 

Table 28: 

Alternate function AF8 to AF15

– New  t

VBAT_BOR_sampling

 in 

Table 34: Embedded reset and power control block 

characteristics

– C

S_PARA

 in 

Table 79: LSE oscillator characteristics (f

LSE

 = 32.768 kHz)

Figure 32: Typical application with a 32.768 kHz crystal

17-Mar-2022

5

Updated:
– PSSI, GPIOs, and capacitive sensing in 

Table 2: STM32U585xx features and 

peripheral counts

– Figure 1: STM32U585xx block diagram

– V

BAT

 in 

Section 3.9.1: Power supply schemes

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Revision history

345

17-Mar-2022

5 (cont’d)

– Backup domain in 

Figure 2 

and 

Figure 3: STM32U575xx power supply overview 

(without SMPS)

– IWDG  in 

Table 10: Functionalities depending on the working mode

– New sentence beg. of 

Section 3.25: Octo-SPI interface (OCTOSPI) 

– Section 3.25.1: OCTOSPI TrustZone security
– Figure 9: UFQFPN48_SMPS pinout 

– PB2 I/O structure in 

Table 26: STM32U575xx pin definitions

– Notes of 

Table 50: Current consumption in Stop 1 mode on LDO 

– Table 51: Current consumption during wakeup from Stop 1 mode on LDO

– Notes of 

Table 52: Current consumption in Stop 1 mode on SMPS 

– Table 53: Current consumption during wakeup from Stop 1 mode on SMPS

– Table 

SRAM static power consumption in Stop 2 when supplied by LDO 

moved 

– Notes of 

Table 54: Current consumption in Stop 2 mode on LDO 

– Table 56: Current consumption during wakeup from Stop 2 mode on LDO 

– Table 

SRAM static power consumption in Stop 2 when supplied by SMPS 

moved 

– Table 59: Current consumption during wakeup from Stop 2 mode on SMPS 

– Notes of 

Table 57: Current consumption in Stop 2 mode on SMPS

– Table 

SRAM static power consumption in Stop 3 when supplied by LDO 

moved 

– Table 62: Current consumption during wakeup from Stop 3 mode on LDO

– Table 

SRAM static power consumption in Stop 3 when supplied by SMPS 

moved 

– Notes of 

Table 63: Current consumption in Stop 3 mode on SMPS 

– Table 65: Current consumption during wakeup from Stop 3 mode on SMPS 
– Table 67: Current consumption during wakeup from Standby mode 

– Notes of 

Table 68: Current consumption in Shutdown mode 

– Table 69: Current consumption during wakeup from Shutdown mode 

– t

wu(Sleep) 

and notes of 

Table 72: Low-power mode wakeup timings on LDO 

– Notes 

Table 74: Regulator mode transition times 

– Output driving current 

– Notes of 

Table 93: Output voltage characteristics

– New 

Table 94: Output voltage characteristics for FT_t I/Os in V

BAT 

mode

– Notes of 

Table 95: Output AC characteristics, HSLV OFF (all I/Os except FT_c)

– Notes of 

Table 96: Output AC characteristics, HSLV ON (all I/Os except FT_c) 

– Table 98: Output AC characteristics for FT_t I/Os in V

BAT 

mode

– f

AHB_CAL 

removed from 

Table 102: 14-bit ADC1 characteristics

– Table 112: DAC characteristics 

– R

Load 

and en in 

Table 116: OPAMP characteristics

– New 

Figure 44: OPAMP voltage noise density, normal mode, R

LOAD 

= 3.9 k

 

and 

Figure 45: OPAMP voltage noise density, low-power mode, R

LOAD 

= 20 k

 

– t

Lv(NOE_NE) 

in 

Table 129: Asynchronous multiplexed PSRAM/NOR read timings

– Section 6.2: LQFP48 package information
– Section 6.3: LQFP64 package information
– Section 6.5: LQFP100 package information
– Section 6.7: LQFP144 package information

– Disclaimer 

Table 166. Document revision history (continued)

Date

Revision

Changes

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6

Added:

– Section 8: Important security notice

Updated:

– Up to 22 capacitive sensing channels
– Section 2: Description
– Table 2.: STM32U575xx features and peripheral counts
– Section 3.36: Touch sensing controller (TSC)

– TSC_G3_IO1/TSC_G1_IO4 are removed from PC2/PC3 in 

Table 26.: 

STM32U575xx pin definitions

 and 

Table 28.: Alternate function AF8 to AF15

– Table 71.: Typical dynamic current consumption of peripherals
– Table 89: EMI characteristics for f

HSE

 = 8 MHz and f

HCLK

 = 160 MHz

– Minimum value added for PSSR in 

Table 117.: OPAMP characteristics

– Disclaimer

27-Mar-2023

7

Updates related to revisions other than X:

– Features
– Table 26: Legend/abbreviations used in the pinout table
– Table 27: STM32U585xx pin definitions
– Table 52: Current consumption in Stop 1 mode on LDO
– Table 54: Current consumption in Stop 1 mode on SMPS
– Table 56: Current consumption in Stop 2 mode on LDO
– Table 59: Current consumption in Stop 2 mode on SMPS
– Table 62: Current consumption in Stop 3 mode on LDO
– Table 65: Current consumption in Stop 3 mode on SMPS
– Table 68: Current consumption in Standby mode
– Table 70: Current consumption in Shutdown mode
– Table 72: Current consumption in V

BAT

 mode

– Table 80: HSE oscillator characteristics
– Table 81: LSE oscillator characteristics (f

LSE

 = 32.768 kHz)

– Table 95: I/O static characteristics
– Table 96: Output voltage characteristics (all I/Os except FT_t I/Os in VBAT mode, 

and FT_o I/Os)

– Table 97: Output voltage characteristics for FT_t I/Os in V

BAT

 mode, and for FT_o 

I/Os

– Table 98: Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in VBAT 

mode and FT_o I/Os)

– Table 101: Output AC characteristics for FT_t I/Os in V

BAT

 mode, and for FT_o I/Os

– Table 107: 14-bit ADC1 accuracy

Table 166. Document revision history (continued)

Date

Revision

Changes

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27-Mar-2023

7 (cont’d)

Other updates:

– Figure 2: STM32U5875xQ power supply overview (with SMPS)
– Figure 3: STM32U585xx power supply overview (without SMPS)
– Section 3.9.1: Power supply schemes
– Section 3.9.3: Low-power modes
– Table 15: ADC features
– Section 5.1.2: Typical values
– Table 31: Current characteristics
– Table 33: General operating conditions
– Table 34: Operating conditions at power-up/power-down
– Table 35: Embedded reset and power control block characteristics
– Table 37: Embedded internal voltage reference
– Table 73: Typical dynamic current consumption of peripherals
– Table 74: Low-power mode wake-up timings on LDO
– Table 78: High-speed external user clock characteristics
– Output driving current
– Section 5.3.30: DCMI characteristics
– Section 5.3.31: PSSI characteristics
– Table 142: OCTOSPI characteristics in SDR mode
– Table 143: OCTOSPI characteristics in DTR mode (no DQS)
– Table 144: OCTOSPI characteristics in DTR mode (with DQS)/HyperBus
– Table 149: USART characteristics
– Table 150: SPI characteristics
– Table 151: SAI characteristics

Typos fix and minor changes in overall document

Added:
– USB logo in 

Section 1: Introduction

– Figure 29: AC timing diagram for high-speed external clock source (analog mode)
– Section 6.9.1: Reference documents

04-Aug-2023

8

Updated:

– Figure 1: STM32U585xx block diagram
– Section 3.9.5: VBAT operation
– Section 3.10: Peripheral interconnect matrix
– Section 5.1.6: Power supply scheme
– Table 38: Current consumption in Run mode on LDO, code with data processing 

running from Flash memory, ICACHE ON (1-way), prefetch ON

– Table 53: Current consumption during wake-up from Stop 1 mode on LDO
– Table 55: Current consumption during wake-up from Stop 1 mode on SMPS
– Table 58: Current consumption during wake-up from Stop 2 mode on LDO
– Table 61: Current consumption during wake-up from Stop 2 mode on SMPS

Table 166. Document revision history (continued)

Date

Revision

Changes

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8 (cont’d)

– Table 64: Current consumption during wake-up from Stop 3 mode on LDO
– Table 67: Current consumption during wake-up from Stop 3 mode on SMPS
– Table 69: Current consumption during wake-up from Standby mode
– Table 71: Current consumption during wake-up from Shutdown mode
– Table 74: Low-power mode wake-up timings on LDO
– Table 75: Low-power mode wake-up timings on SMPS
– Table 76: Regulator mode transition times
– Table 78: High-speed external user clock characteristics

Increased HSE consumption during startup from 8 µA to 8 mA

 in Table 80: HSE 

oscillator characteristics

– Table 81: LSE oscillator characteristics (f

LSE

 = 32.768 kHz)

– Table 97: Output voltage characteristics for FT_t I/Os in V

BAT

 mode, and for FT_o 

I/Os

– Table 101: Output AC characteristics for FT_t I/Os in V

BAT

 mode, and for FT_o I/Os

– t

CAL

 and t

OFF_CAL

 values in Table 105: 14-bit ADC1 characteristics

– t

OFF_CAL

 values in Table 108: 12-bit ADC4 characteristics

– Note added in 

Table 106: Maximum RAIN for 14-bit ADC1

 and 

Table 109: Maximum 

RAIN for 12-bit ADC4

– Section 5.3.28: Temperature and backup domain supply thresholds monitoring
– Figure 74: USART timing diagram in SPI master mode
– Figure 75: USART timing diagram in SPI slave mode
– Figure 76: SPI timing diagram - slave mode and CPHA = 0
– Figure 77: SPI timing diagram - slave mode and CPHA = 1
– Figure 78: SPI timing diagram - master mode
– Figure 79: SAI master timing diagram
– Figure 80: SAI slave timing diagram
– Section 6.1: UFQFPN48 package information (A0B9)
– Section 6.2: LQFP48 package information (5B)
– Section 6.3: LQFP64 package information (5W)
– Section 6.4: WLCSP90 package information (B01C)
– Section 6.5: LQFP100 package information (1L)
– Section 6.6: UFBGA132 package information (A0G8)
– Section 6.7: LQFP144 package information (1A)
– Section 6.8: UFBGA169 package information (A0YV)

Added:

– Table 5.3.4: SMPS characteristics

Table 166. Document revision history (continued)

Date

Revision

Changes

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19-Feb-2024

9

Updated:

– Up to 22 communication peripherals in Features
– Replaced “o” by “-” for Backup domain voltage and temperature monitoring in 

Table 10: Functionalities depending on the working mode

– Figure 61: NAND controller waveforms for read access
– Figure 62: NAND controller waveforms for write access
– Figure 74: USART timing diagram in SPI master mode
– Figure 75: USART timing diagram in SPI slave mode
– Table 78: Low-speed external user clock characteristics
– Table 101: NRST pin characteristics

Added:

SPI mode in Table 22: USART, UART, and LPUART features,

 

Section 3.45.1: Universal synchronous/asynchronous receiver transmitter 
(USART/UART), and Section 5.3.38: USART (SPI mode) characteristics

05-Jul-2024

10

Updated:

Table 26: STM32U575xx pin definitions

Table 27: Alternate function AF0 to AF7

Table 28: Alternate function AF8 to AF15

Table 51: Current consumption in Stop 1 mode on LDO

Table 53: Current consumption in Stop 1 mode on SMPS

Table 58: Current consumption in Stop 2 mode on SMPS

Table 61: Current consumption in Stop 3 mode on LDO

Table 64: Current consumption in Stop 3 mode on SMPS

Note:

Table 26

Table 27

 and 

Table 28

 updates do not require any 

hardware or firmware change.

Chapter 3.4: Embedded flash memory

Section 3.9.1: Power supply schemes

– Notes in 

Section 5.2: Absolute maximum ratings

Added:

– Sustainable technology logo in 

Features

Figure 34: HSI16 frequency versus temperature and V

DD

Table 166. Document revision history (continued)

Date

Revision

Changes

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